Timing errors in LDPC decoding computations with overscaled supply voltage

Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling (VOS) in their implementation to save energy. In this paper, the impact of VOS on...

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Bibliographic Details
Published in:2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) pp. 201 - 206
Main Authors: Sedighi, Behnam, Anthapadmanabhan, N. Prasanth, Suvakovic, Dusan
Format: Conference Proceeding
Language:English
Published: ACM 01.08.2014
Subjects:
Arithmetic and signal processing circuits
Computation errors
Decoding
Delays
Error-resilience
Integrated circuit modeling
Noisy decoder
Parity check codes
Registers
Simulation
Voltage over-scaling
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Summary:Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling (VOS) in their implementation to save energy. In this paper, the impact of VOS on timing errors is characterized for a typical min-sum LDPC decoder architecture using circuit simulations. Failure modes are analyzed for arithmetic circuits performing variable and check node computations. It is shown that a rather unconventional register placement in the variable node unit is beneficial for voltage scaling, and that the check node unit may be designed such that only the least significant bits are more likely to experience errors. Insights into timing error characteristics obtained through this analysis can be used to estimate the limits of voltage scaling and associated energy saving in practical LDPC decoder designs.
DOI:10.1145/2627369.2627638