Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

In this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications.Processes are statically scheduled and communications are performed using the time-triggered protocol.We use process re-execution and replication for tolerating transie...

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Vydané v:Design, Automation and Test in Europe s. 864 - 869
Hlavní autori: Izosimov, Viacheslav, Pop, Paul, Eles, Petru, Peng, Zebo
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Edícia:ACM Conferences
Predmet:
Communication system control
Computer science
Computer systems organization > Embedded and cyber-physical systems
Computer systems organization > Real-time systems
Computing methodologies > Artificial intelligence > Search methodologies > Heuristic function construction
Datavetenskap
Design optimization
Embedded system
embedded systems
Fault detection
Fault tolerant systems
fault-tolerance
General and reference > Cross-computing tools and techniques > Performance
Hardware > Hardware test
Hardware > Robustness
Information technology
Informationsteknik
Job shop scheduling
mapping
Protocols
re-execution
Real time systems
replication
scheduling
Software architecture
TECHNOLOGY
TEKNIKVETENSKAP
Time division multiple access
time-triggered
ISBN:9780769522883, 0769522882
ISSN:1530-1591
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Popis
Shrnutí:In this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications.Processes are statically scheduled and communications are performed using the time-triggered protocol.We use process re-execution and replication for tolerating transient faults.Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied.We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources.The developed algorithms are evaluated using extensive experiments, including a real-life example.
Bibliografia:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.116