Power-efficient LDPC code decoder architecture

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression techni...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007 s. 359 - 362
Hlavní autori:	Shimizu, K, Togawa, N, Ikenaga, T, Goto, S
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 27.08.2007
Predmet:	clock gating Clocks Computer architecture Convergence FIFO buffer intermediate message compression technique Iterative algorithms Iterative decoding LDPC decoder message-passing schedule Parity check codes Power dissipation Read-write memory Shift registers Throughput
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Popis
Shrnutí:	This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.
DOI:	10.1145/1283780.1283858