Power-efficient LDPC code decoder architecture

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression techni...

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Veröffentlicht in:	ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007 S. 359 - 362
Hauptverfasser:	Shimizu, K, Togawa, N, Ikenaga, T, Goto, S
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 27.08.2007
Schlagworte:	clock gating Clocks Computer architecture Convergence FIFO buffer intermediate message compression technique Iterative algorithms Iterative decoding LDPC decoder message-passing schedule Parity check codes Power dissipation Read-write memory Shift registers Throughput
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