Power-efficient LDPC code decoder architecture

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression techni...

Full description

Bibliographic Details

Published in:	ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007 pp. 359 - 362
Main Authors:	Shimizu, K, Togawa, N, Ikenaga, T, Goto, S
Format:	Conference Proceeding
Language:	English
Published:	IEEE 27.08.2007
Subjects:	clock gating Clocks Computer architecture Convergence FIFO buffer intermediate message compression technique Iterative algorithms Iterative decoding LDPC decoder message-passing schedule Parity check codes Power dissipation Read-write memory Shift registers Throughput
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!