Shimizu, K., Togawa, N., Ikenaga, T., & Goto, S. (2007, August 27). Power-efficient LDPC code decoder architecture. ISLPED '07 : proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007, 359-362. https://doi.org/10.1145/1283780.1283858
Citácia podle Chicago (17th ed.)Shimizu, K., N. Togawa, T. Ikenaga, a S. Goto. "Power-efficient LDPC Code Decoder Architecture." ISLPED '07 : Proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007 27 Aug. 2007: 359-362. https://doi.org/10.1145/1283780.1283858.
Citácia podľa MLA (8th ed.)Shimizu, K., et al. "Power-efficient LDPC Code Decoder Architecture." ISLPED '07 : Proceedings of the International Symposium on Low Power Electronics and Design : Portland, Oregon, USA, August 27-29, 2007, 27 Aug. 2007, pp. 359-362, https://doi.org/10.1145/1283780.1283858.