Delay-optimal technology mapping by DAG covering

We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this n...

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Veröffentlicht in:DAC 98: DAC: 35th Annual ACM/IEEE Design Automation Conference S. 348 - 351
Hauptverfasser: Kukimoto, Yuji, Brayton, Robert K., Sawkar, Prashant
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 01.01.1998
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Algorithm design and analysis
Applied computing > Physical sciences and engineering > Engineering
Circuits
Delay
Design automation
Dynamic programming
Field programmable gate arrays
Hardware > Emerging technologies
Hardware > Robustness
Hardware > Very large scale integration design
Laboratories
Mathematics of computing > Discrete mathematics
Mathematics of computing > Mathematical software
Permission
Theory of computation > Design and analysis of algorithms > Data structures design and analysis > Pattern matching
Tree graphs
Vegetation mapping
relaxed pins
supply-demand
global routing
quadratic placement
routing models
congestion
ISBN:0897919645, 9780897919647
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0897919645
9780897919647
DOI:10.1145/277044.277142