Delay-optimal technology mapping by DAG covering
We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this n...
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| Published in: | DAC 98: DAC: 35th Annual ACM/IEEE Design Automation Conference pp. 348 - 351 |
|---|---|
| Main Authors: | , , |
| Format: | Conference Proceeding |
| Language: | English |
| Published: |
New York, NY, USA
ACM
01.01.1998
IEEE |
| Series: | ACM Conferences |
| Subjects: | |
| ISBN: | 0897919645, 9780897919647 |
| Online Access: | Get full text |
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| Abstract | We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach. |
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| AbstractList | We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach. |
| Author | Brayton, Robert K. Sawkar, Prashant Kukimoto, Yuji |
| Author_xml | – sequence: 1 givenname: Yuji surname: Kukimoto fullname: Kukimoto, Yuji organization: Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA – sequence: 2 givenname: Robert K. surname: Brayton fullname: Brayton, Robert K. organization: Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA – sequence: 3 givenname: Prashant surname: Sawkar fullname: Sawkar, Prashant organization: Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR |
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| Copyright | 1998 ACM |
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| DOI | 10.1145/277044.277142 |
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| Keywords | relaxed pins supply-demand global routing quadratic placement routing models congestion |
| Language | English |
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| Snippet | We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay... |
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| SubjectTerms | Algorithm design and analysis Applied computing -- Physical sciences and engineering -- Engineering Circuits Delay Design automation Dynamic programming Field programmable gate arrays Hardware -- Emerging technologies Hardware -- Robustness Hardware -- Very large scale integration design Laboratories Mathematics of computing -- Discrete mathematics Mathematics of computing -- Mathematical software Permission Theory of computation -- Design and analysis of algorithms -- Data structures design and analysis -- Pattern matching Tree graphs Vegetation mapping |
| Title | Delay-optimal technology mapping by DAG covering |
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