Critical path analysis using a dynamically bounded delay model
This paper focuses on static timing analysis in the presence of capacitive coupling. We propose a novel gate delay model, the dynamically bounded delay model. In contrast to the min-max or bounded delay model which assumes a fixed delay range, [dmin, dmax], for each circuit component, our new model...
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| Published in: | 37th Design Automation Conference, 2000 pp. 260 - 265 |
|---|---|
| Main Author: | |
| Format: | Conference Proceeding |
| Language: | English |
| Published: |
New York, NY, USA
ACM
01.01.2000
IEEE |
| Series: | ACM Conferences |
| Subjects: |
Mathematics of computing
> Mathematical analysis
> Mathematical optimization
> Mixed discrete-continuous optimization
> Integer programming
Social and professional topics
> Professional topics
> Management of computing and information systems
> Project and people management
> Project management techniques
|
| ISBN: | 9781581131871, 1581131879 |
| Online Access: | Get full text |
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| Abstract | This paper focuses on static timing analysis in the presence of capacitive coupling. We propose a novel gate delay model, the dynamically bounded delay model. In contrast to the min-max or bounded delay model which assumes a fixed delay range, [dmin, dmax], for each circuit component, our new model allows for the specification of delay variations and the conditions upon which the variations will hold. Novel static timing analysis algorithms can thus dynamically bound the delays. To demonstrate the effectiveness of this model and approach, we use our model to perform critical path analysis in the presence of capacitive coupling. Our experiments show that our approach avoids pessimism when compared to PERT analysis assuming worst case capacitive coupling. |
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| AbstractList | This paper focuses on static timing analysis in the presence of capacitive coupling. We propose a novel gate delay model, the dynamically bounded delay model. In contrast to the min-max or bounded delay model which assumes a fixed delay range, [dmin, dmax], for each circuit component, our new model allows for the specification of delay variations and the conditions upon which the variations will hold. Novel static timing analysis algorithms can thus dynamically bound the delays. To demonstrate the effectiveness of this model and approach, we use our model to perform critical path analysis in the presence of capacitive coupling. Our experiments show that our approach avoids pessimism when compared to PERT analysis assuming worst case capacitive coupling. |
| Author | Hassoun, Soha |
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| SubjectTerms | Algorithm design and analysis Applied computing -- Physical sciences and engineering -- Engineering Circuit analysis Computer systems organization -- Dependable and fault-tolerant systems and networks Coupling circuits Delay Digital circuits General and reference -- Cross-computing tools and techniques -- Performance Hardware -- Emerging technologies Hardware -- Robustness Hardware -- Very large scale integration design Heuristic algorithms Mathematics of computing -- Mathematical analysis -- Mathematical optimization -- Mixed discrete-continuous optimization -- Integer programming Networks -- Network performance evaluation Performance analysis Permission Social and professional topics -- Professional topics -- Management of computing and information systems -- Project and people management -- Project management techniques Theory of computation -- Design and analysis of algorithms -- Mathematical optimization -- Mixed discrete-continuous optimization -- Integer programming Timing Wires |
| Title | Critical path analysis using a dynamically bounded delay model |
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