A Synthesizable IP Core for DVB-S2 LDPC Code Decoding

The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative...

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Veröffentlicht in:Design, Automation and Test in Europe S. 100 - 105
Hauptverfasser: Kienle, Frank, Brack, Torben, Wehn, Norbert
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Washington, DC, USA IEEE Computer Society 01.01.2005
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Base stations
Channel coding
CMOS technology
Code standards
Computing methodologies > Artificial intelligence > Computer vision > Computer vision problems > Video segmentation
Computing methodologies > Artificial intelligence > Computer vision > Computer vision tasks > Video summarization
Computing methodologies > Artificial intelligence > Computer vision > Image and video acquisition
Data processing
Digital video broadcasting
Hardware
Hardware > Hardware validation
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
Iterative decoding
Mathematics of computing > Information theory
Mathematics of computing > Information theory > Coding theory
Networks > Network protocols
Parity check codes
Security and privacy > Cryptography > Mathematical foundations of cryptography
Throughput
ISBN:9780769522883, 0769522882
ISSN:1530-1591
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates with a block size of 64800 which allows a transmission close to the theoretical limits. The decoding of LDPC is an iterative process. For DVB-S2 about 300000 messages are processed and reordered in each of the 30 iterations. These huge data processing and storage requirements are a real challenge for the decoder hardware realization, which has to fulfill the specified throughput of 255MBit/s for base station applications. In this paper we will show, to the best of our knowledge, the first published IP LDPC decoder core for the DVB-S2 standard. We present a synthesizable IP block based on ST Microelectronics 0:13µm CMOS technology.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.39