DTexL: Decoupled Raster Pipeline for Texture Locality
Contemporary GPU architectures have multiple shader cores and a scheduler that distributes work (threads) among them, focusing on load balancing. These load balancing techniques favor thread distributions that are detrimental to texture memory locality for graphics applications in the L1 Texture Cac...
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| Vydáno v: | 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) s. 213 - 227 |
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01.10.2022
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| Abstract | Contemporary GPU architectures have multiple shader cores and a scheduler that distributes work (threads) among them, focusing on load balancing. These load balancing techniques favor thread distributions that are detrimental to texture memory locality for graphics applications in the L1 Texture Caches. Texture memory accesses make up the majority of the traffic to the memory hierarchy in typical low power graphics architectures. This paper focuses on improving the L1 Texture cache locality by focusing on a new workload scheduler by exploring various methods to group the threads, assign the groups to shader cores and also to reorder threads without violating the correctness of the pipeline. To overcome the resulting load imbalance, we also propose a minor modification in the GPU architecture that helps translate the improvement in cache locality to an improvement in the GPU's performance. We propose DTexL that envelops these ideas and evaluate it over a benchmark suite of ten commercial games, to obtain a 46.8% decrease in L2 Accesses, a 19.3% increase in performance and a 6.3% decrease in total GPU energy. All this with a negligible overhead. |
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| AbstractList | Contemporary GPU architectures have multiple shader cores and a scheduler that distributes work (threads) among them, focusing on load balancing. These load balancing techniques favor thread distributions that are detrimental to texture memory locality for graphics applications in the L1 Texture Caches. Texture memory accesses make up the majority of the traffic to the memory hierarchy in typical low power graphics architectures. This paper focuses on improving the L1 Texture cache locality by focusing on a new workload scheduler by exploring various methods to group the threads, assign the groups to shader cores and also to reorder threads without violating the correctness of the pipeline. To overcome the resulting load imbalance, we also propose a minor modification in the GPU architecture that helps translate the improvement in cache locality to an improvement in the GPU's performance. We propose DTexL that envelops these ideas and evaluate it over a benchmark suite of ten commercial games, to obtain a 46.8% decrease in L2 Accesses, a 19.3% increase in performance and a 6.3% decrease in total GPU energy. All this with a negligible overhead. |
| Author | Parcerisa, Joan-Manuel Gonzalez, Antonio Joseph, Diya Aragon, Juan L. |
| Author_xml | – sequence: 1 givenname: Diya surname: Joseph fullname: Joseph, Diya organization: Universitat Politècnica de Catalunya,Barcelona,Spain – sequence: 2 givenname: Juan L. surname: Aragon fullname: Aragon, Juan L. organization: Universidad de Murcia,Murcia,Spain – sequence: 3 givenname: Joan-Manuel surname: Parcerisa fullname: Parcerisa, Joan-Manuel organization: Universitat Politècnica de Catalunya,Barcelona,Spain – sequence: 4 givenname: Antonio surname: Gonzalez fullname: Gonzalez, Antonio organization: Universitat Politècnica de Catalunya,Barcelona,Spain |
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| Snippet | Contemporary GPU architectures have multiple shader cores and a scheduler that distributes work (threads) among them, focusing on load balancing. These load... |
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| SubjectTerms | Caches Focusing GPU Graphics Graphics processing units Instruction sets Low-power Microarchitecture Pipelines Scheduling Texture Locality Upper bound |
| Title | DTexL: Decoupled Raster Pipeline for Texture Locality |
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