Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in 2014, where repeatedly accessing data in a DRAM row can cause bit flips in nearby rows. The RowHammer vulnerability has since garnered significant interest in both computer architecture and computer security...
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| Vydáno v: | 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) s. 638 - 651 |
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IEEE
01.05.2020
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| Abstract | RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in 2014, where repeatedly accessing data in a DRAM row can cause bit flips in nearby rows. The RowHammer vulnerability has since garnered significant interest in both computer architecture and computer security research communities because it stems from physical circuit-level interference effects that worsen with continued DRAM density scaling. As DRAM manufacturers primarily depend on density scaling to increase DRAM capacity, future DRAM chips will likely be more vulnerable to RowHammer than those of the past. Many RowHammer mitigation mechanisms have been proposed by both industry and academia, but it is unclear whether these mechanisms will remain viable solutions for future devices, as their overheads increase with DRAM's vulnerability to RowHammer.In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408\timesDDR3, 652\timesDDR4, and 520\timesLPDDR4) from 300 DRAM modules (60\timesDDR3, 110\timesDDR4, and 130\timesLPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three major DRAM manufacturers. Our studies definitively show that newer DRAM chips are more vulnerable to RowHammer: as device feature size reduces, the number of activations needed to induce a RowHammer bit flip also reduces, to as few as 9.6 k (4.8k to two rows each) in the most vulnerable chip we tested.We evaluate five state-of-the-art RowHammer mitigation mechanisms using cycle-accurate simulation in the context of real data taken from our chips to study how the mitigation mechanisms scale with chip vulnerability. We find that existing mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices given our observed trends of RowHammer vulnerability. Thus, it is critical to research more effective solutions to RowHammer. |
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| AbstractList | RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in 2014, where repeatedly accessing data in a DRAM row can cause bit flips in nearby rows. The RowHammer vulnerability has since garnered significant interest in both computer architecture and computer security research communities because it stems from physical circuit-level interference effects that worsen with continued DRAM density scaling. As DRAM manufacturers primarily depend on density scaling to increase DRAM capacity, future DRAM chips will likely be more vulnerable to RowHammer than those of the past. Many RowHammer mitigation mechanisms have been proposed by both industry and academia, but it is unclear whether these mechanisms will remain viable solutions for future devices, as their overheads increase with DRAM's vulnerability to RowHammer.In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408\timesDDR3, 652\timesDDR4, and 520\timesLPDDR4) from 300 DRAM modules (60\timesDDR3, 110\timesDDR4, and 130\timesLPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three major DRAM manufacturers. Our studies definitively show that newer DRAM chips are more vulnerable to RowHammer: as device feature size reduces, the number of activations needed to induce a RowHammer bit flip also reduces, to as few as 9.6 k (4.8k to two rows each) in the most vulnerable chip we tested.We evaluate five state-of-the-art RowHammer mitigation mechanisms using cycle-accurate simulation in the context of real data taken from our chips to study how the mitigation mechanisms scale with chip vulnerability. We find that existing mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices given our observed trends of RowHammer vulnerability. Thus, it is critical to research more effective solutions to RowHammer. |
| Author | Patel, Minesh Yaglikci, A. Giray Azizi, Roknoddin Kim, Jeremie S. Mutlu, Onur Orosa, Lois Hassan, Hasan |
| Author_xml | – sequence: 1 givenname: Jeremie S. surname: Kim fullname: Kim, Jeremie S. organization: ETH Zürich – sequence: 2 givenname: Minesh surname: Patel fullname: Patel, Minesh organization: ETH Zürich – sequence: 3 givenname: A. Giray surname: Yaglikci fullname: Yaglikci, A. Giray organization: ETH Zürich – sequence: 4 givenname: Hasan surname: Hassan fullname: Hassan, Hasan organization: ETH Zürich – sequence: 5 givenname: Roknoddin surname: Azizi fullname: Azizi, Roknoddin organization: ETH Zürich – sequence: 6 givenname: Lois surname: Orosa fullname: Orosa, Lois organization: ETH Zürich – sequence: 7 givenname: Onur surname: Mutlu fullname: Mutlu, Onur organization: ETH Zürich |
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| Snippet | RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in 2014, where repeatedly accessing data in a DRAM row can cause bit... |
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| SubjectTerms | Computer architecture Computer security DRAM chips Industries Interference Performance evaluation Prevention and mitigation Protection |
| Title | Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques |
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