Post-routing redundant via insertion for yield/reliability improvement

Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/reliability is to add redundant vias. In this paper we study the problem of post-routing redundant via insertion and formulate...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of the 2006 Asia and South Pacific Design Automation Conference pp. 303 - 308
Main Authors: Lee, Kuang-Yao, Wang, Ting-Chi
Format: Conference Proceeding
Language:English
Published: Piscataway, NJ, USA IEEE Press 01.01.2006
Series:ACM Conferences
Subjects:
Computing methodologies > Artificial intelligence > Search methodologies > Heuristic function construction
Hardware
Hardware > Electronic design automation > Physical design (EDA) > Partitioning and floorplanning
Hardware > Electronic design automation > Physical design (EDA) > Placement
Hardware > Electronic design automation > Physical design (EDA) > Wire routing
Hardware > Hardware validation
Mathematics of computing > Discrete mathematics > Graph theory > Paths and connectivity problems
ISBN:9780780394513, 0780394518
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/reliability is to add redundant vias. In this paper we study the problem of post-routing redundant via insertion and formulate it as a maximum independent set (MIS) problem. We present an efficient graph construction algorithm to model the problem, and an effective MIS heuristic to solve the problem. The experimental results show that our MIS heuristic inserts more redundant vias and distributes them more uniformly among via layers than a commercial tool and an existing method. The number of inserted redundant vias can be increased by up to 21.24%. Besides, since redundant vias can be classified into on-track and off-track ones, and on-track ones have better electrical properties, we also present two methods (one is modified from the MIS heuristic, and the other is applied as a post processor) to increase the amount of on-track redundant vias. The experimental results indicate that both methods perform very well.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780780394513
0780394518
DOI:10.1145/1118299.1118376