A design methodology for domain-optimized power-efficient supercomputing
As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code,...
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| Veröffentlicht in: | Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis S. 1 - 12 |
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| Sprache: | Englisch |
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New York, NY, USA
ACM
14.11.2009
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| Schriftenreihe: | ACM Conferences |
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| ISBN: | 1605587443, 9781605587448 |
| ISSN: | 2167-4329 |
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| Abstract | As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software cotuning as a novel approach for system design, in which traditional architecture space exploration is tightly coupled with software auto-tuning for delivering substantial improvements in area and power efficiency. We demonstrate the proposed methodology by exploring the parameter space of a Tensilica-based multi-processor running three of the most heavily used kernels in scientific computing, each with widely varying micro-architectural requirements: sparse matrix vector multiplication, stencil-based computations, and general matrix-matrix multiplication. Results demonstrate that co-tuning significantly improves hardware area and energy efficiency -- a key driver for next generation of HPC system design. |
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| AbstractList | As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance. Recently, static benchmark codes have been used to find a power efficient architecture. Unfortunately, because compilers generate sub-optimal code, benchmark performance can be a poor indicator of the performance potential of architecture design points. Therefore, we present hardware/software cotuning as a novel approach for system design, in which traditional architecture space exploration is tightly coupled with software auto-tuning for delivering substantial improvements in area and power efficiency. We demonstrate the proposed methodology by exploring the parameter space of a Tensilica-based multi-processor running three of the most heavily used kernels in scientific computing, each with widely varying micro-architectural requirements: sparse matrix vector multiplication, stencil-based computations, and general matrix-matrix multiplication. Results demonstrate that co-tuning significantly improves hardware area and energy efficiency -- a key driver for next generation of HPC system design. |
| Author | Mohiyuddin, Marghoob Wawrzynek, John Murphy, Mark Shalf, John Williams, Samuel Oliker, Leonid |
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| Snippet | As power has become the pre-eminent design constraint for future HPC systems, computational efficiency is being emphasized over simply peak performance.... |
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| SubjectTerms | Codes Computer architecture Computer systems organization -- Architectures -- Distributed architectures -- Grid computing Computer systems organization -- Architectures -- Parallel architectures -- Multicore architectures Computer systems organization -- Architectures -- Serial architectures -- Superscalar architectures Computing methodologies -- Modeling and simulation -- Simulation types and techniques -- Massively parallel and high-performance simulations Costs Energy efficiency General and reference -- Cross-computing tools and techniques -- Design General and reference -- Cross-computing tools and techniques -- Performance Hardware Hardware -- Electronic design automation -- Modeling and parameter extraction Kernel Optimization Software Software and its engineering -- Software organization and properties -- Software system structures -- Distributed systems organizing principles -- Grid computing System analysis and design Tuning |
| Title | A design methodology for domain-optimized power-efficient supercomputing |
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