Software-Controlled Priority Characterization of POWER5 Processor
Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded dual-core chip. In each SMT core, the IBM POWER5 features two levels of thr...
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| Published in: | 2008 International Symposium on Computer Architecture pp. 415 - 426 |
|---|---|
| Main Authors: | , , , , , |
| Format: | Conference Proceeding Publication |
| Language: | English |
| Published: |
Washington, DC, USA
IEEE Computer Society
01.06.2008
IEEE Institute of Electrical and Electronics Engineers (IEEE) |
| Series: | ACM Conferences |
| Subjects: | |
| ISBN: | 9780769531748, 0769531741 |
| ISSN: | 1063-6897 |
| Online Access: | Get full text |
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