The StageNet fabric for constructing resilient multicore systems

Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leading to increasing operating temperatures and current densities. Given that most wearout mechanisms that plague semiconducto...

Full description

Saved in:
Bibliographic Details
Published in:2008 41st IEEE/ACM International Symposium on Microarchitecture pp. 141 - 151
Main Authors: Gupta, Shantanu, Feng, Shuguang, Ansari, Amin, Blome, Jason, Mahlke, Scott
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 08.11.2008
IEEE
Series:ACM Conferences
Subjects:
Computer systems organization
Computer systems organization > Dependable and fault-tolerant systems and networks
Current density
Fabrics
General and reference
General and reference > Cross-computing tools and techniques
General and reference > Cross-computing tools and techniques > Performance
Hardware
Hardware > Hardware validation
Multicore processing
Networks
Networks > Network performance evaluation
Performance gain
Redundancy
Semiconductor devices
Space technology
Temperature
Tin
Voltage
ISBN:9781424428366, 142442836X
ISSN:1072-4451
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leading to increasing operating temperatures and current densities. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Consequently, high reliability and fault tolerance, which have traditionally been subjects of interest for high-end server markets, are now getting emphasis in the mainstream desktop and embedded systems space. The popular solution for this has been the use of redundancy at a coarse granularity, such as dual/triple modular redundancy. In this work, we challenge the practice of coarse-granularity redundancy by identifying its inability to scale to high failure rate scenarios and investigating the advantages of finer-grained configurations. To this end, this paper presents and evaluates a highly reconfigurable multicore architecture, named StageNet (SN), that is designed with reliability as its first class design criteria. SN relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of a chip, gracefully degrading performance towards the end of life. Our results show that the proposed SN architecture can perform nearly 50% more cumulative work compared to a traditional multicore.
ISBN:9781424428366
142442836X
ISSN:1072-4451
DOI:10.1109/MICRO.2008.4771786