A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design

In this paper, we present a bottom-up clustering algorithm based on recursive collapsing of small cliques in a graph. The sizes of the small cliques are derived using random graph theory. This clustering algorithm leads to a natural parallel implementation in which multiple processors are used to id...

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Bibliographic Details
Published in:30th ACM/IEEE Design Automation Conference pp. 755 - 760
Main Authors: Cong, Jason, Smith, M'Lissa
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 01.07.1993
Series:ACM Conferences
Subjects:
ISBN:9780897915779, 0897915771
ISSN:0738-100X
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Summary:In this paper, we present a bottom-up clustering algorithm based on recursive collapsing of small cliques in a graph. The sizes of the small cliques are derived using random graph theory. This clustering algorithm leads to a natural parallel implementation in which multiple processors are used to identify clusters simultaneously. We also present a cluster-based partitioning method in which our clustering algorithm is used as a preprocessing step to both the bisection algorithm by Fiduccia and Mattheyses and a ratio-cut algorithm by Wei and Cheng. Our results show that cluster-based partitioning obtains cut sizes up to 49.6% smaller than the bisection algorithm, and obtains ratio cut sizes up to 66.8% smaller than the ratio-cut algorithm. Moreover, we show that cluster-based partitioning produces much stabler results than direct partitioning.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780897915779
0897915771
ISSN:0738-100X
DOI:10.1145/157485.165119