PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research

Technology trends prompting architects to consider greater heterogeneity and hardware specialization have exposed an increasing need for vertically integrated research methodologies that can effectively assess performance, area, and energy metrics of future architectures. However, constructing such...

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Veröffentlicht in:2014 47th Annual IEEE/ACM International Symposium on Microarchitecture S. 280 - 292
Hauptverfasser: Lockhart, Derek, Zibrat, Gary, Batten, Christopher
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.12.2014
Schlagworte:
Computational modeling
Computer architecture
Computers
Hardware
Hardware design languages
Object oriented modeling
Productivity
ISSN:1072-4451
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Zusammenfassung:Technology trends prompting architects to consider greater heterogeneity and hardware specialization have exposed an increasing need for vertically integrated research methodologies that can effectively assess performance, area, and energy metrics of future architectures. However, constructing such a methodology with existing tools is a significant challenge due to the unique languages, design patterns, and tools used in functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. We introduce a new framework called PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for FL, CL, and RTL modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design. While the use of Python as a modeling and framework implementation language provides considerable benefits in terms of productivity, it comes at the cost of significantly longer simulation times. We address this performance-productivity gap with a hybrid JIT compilation and JIT specialization approach. We introduce Sim JIT, a custom JIT specialization engine that automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, we combine Sim JIT with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models, bringing us within 4-6× of optimized C++ code while providing significant benefits in terms of productivity and usability.
ISSN:1072-4451
DOI:10.1109/MICRO.2014.50