A Complete Network-On-Chip Emulation Framework

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional valida...

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Vydané v:	Design, Automation and Test in Europe s. 246 - 251
Hlavní autori:	Genko, N., Atienza, D., Micheli, G. De, Mendias, J. M., Hermida, R., Catthoor, F.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	Washington, DC, USA IEEE Computer Society 07.03.2005 IEEE
Edícia:	ACM Conferences
Predmet:	Computer systems organization > Architectures > Other architectures > Reconfigurable computing Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing Concrete Emulation Field programmable gate arrays Hardware > Communication hardware, interfaces and storage > Buses and high-speed links Hardware > Hardware validation > Functional verification > Simulation and emulation Hardware > Very large scale integration design > Application-specific VLSI designs Hardware design languages Network topology Network-on-a-chip Networks > Network protocols Scalability Silicon Switches Testing
ISBN:	9780769522883, 0769522882
ISSN:	1530-1591
On-line prístup:	Získať plný text
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