A Complete Network-On-Chip Emulation Framework

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional valida...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:Design, Automation and Test in Europe s. 246 - 251
Hlavní autoři: Genko, N., Atienza, D., Micheli, G. De, Mendias, J. M., Hermida, R., Catthoor, F.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Washington, DC, USA IEEE Computer Society 07.03.2005
IEEE
Edice:ACM Conferences
Témata:
Computer systems organization > Architectures > Other architectures > Reconfigurable computing
Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing
Concrete
Emulation
Field programmable gate arrays
Hardware > Communication hardware, interfaces and storage > Buses and high-speed links
Hardware > Hardware validation > Functional verification > Simulation and emulation
Hardware > Very large scale integration design > Application-specific VLSI designs
Hardware design languages
Network topology
Network-on-a-chip
Networks > Network protocols
Scalability
Silicon
Switches
Testing
ISBN:9780769522883, 0769522882
ISSN:1530-1591
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Abstract Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.
AbstractList Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.
Author Mendias, J. M.
Micheli, G. De
Atienza, D.
Hermida, R.
Catthoor, F.
Genko, N.
Author_xml – sequence: 1
  givenname: N.
  surname: Genko
  fullname: Genko, N.
  organization: Stanford University, Palo Alto, USA
– sequence: 2
  givenname: D.
  surname: Atienza
  fullname: Atienza, D.
  organization: DACYA/UCM, Madrid, Spain
– sequence: 3
  givenname: G. De
  surname: Micheli
  fullname: Micheli, G. De
  organization: Stanford University, Palo Alto, USA
– sequence: 4
  givenname: J. M.
  surname: Mendias
  fullname: Mendias, J. M.
  organization: DACYA/UCM, Madrid, Spain
– sequence: 5
  givenname: R.
  surname: Hermida
  fullname: Hermida, R.
  organization: DACYA/UCM, Madrid, Spain
– sequence: 6
  givenname: F.
  surname: Catthoor
  fullname: Catthoor, F.
  organization: IMEC vzw, Leuven, Belgium
BookMark eNqNkDFPwzAQRi1RJErpxMiSATEgJdi-OLHHKm0BqaJLmS0nOYvQJA5xKsS_J1H5Adxyw3v6hndNZq1rkZBbRiPGqHparw6biFMqInFBliqVNE2U4FxKmJE5E0BDJhS7IkvvP-l4oGKWpHMSrYLMNV2NAwZvOHy7_hju2zD7qLpg05xqM1SuDba9aXBiN-TSmtrj8u8vyPt2c8hewt3--TVb7UIDNB1CKaVCAMsp8BJEaUsuTJ5yjgJFaozIWW5VArkpwMSssDamaakslLIwuWGwIA_n3a53Xyf0g24qX2BdmxbdyWtgVFLKk1G8O4sVIuqurxrT_2gGSogkHun9mZqi0blzR68Z1VMxPRXTUzEtRu3xH5rO-wot_AKNKmlw
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
7SC
8FD
JQ2
L7M
L~C
L~D
DOI 10.1109/DATE.2005.5
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
Computer and Information Systems Abstracts
Technology Research Database
ProQuest Computer Science Collection
Advanced Technologies Database with Aerospace
Computer and Information Systems Abstracts – Academic
Computer and Information Systems Abstracts Professional
DatabaseTitle Computer and Information Systems Abstracts
Technology Research Database
Computer and Information Systems Abstracts – Academic
Advanced Technologies Database with Aerospace
ProQuest Computer Science Collection
Computer and Information Systems Abstracts Professional
DatabaseTitleList

Computer and Information Systems Abstracts
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
Computer Science
EndPage 251
ExternalDocumentID 1395564
Genre orig-research
Conference Paper
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
AARBI
ACM
ADPZR
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
GUFHI
OCL
RIB
RIC
RIE
RIL
123
29F
29O
6IH
AAWTH
ABLEC
ADZIZ
CHZPO
FEDTE
IEGSK
IPLJI
KZ1
LMP
M43
RNS
7SC
8FD
JQ2
L7M
L~C
L~D
ID FETCH-LOGICAL-a307t-8889e33f2032d35dfd25ab722e5e57aa5b1bf963bac3a41cff407d9f3d8caba13
IEDL.DBID RIE
ISBN 9780769522883
0769522882
ISICitedReferencesCount 49
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000228086900045&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 1530-1591
IngestDate Thu Jul 10 23:44:55 EDT 2025
Wed Aug 27 02:14:00 EDT 2025
Wed Jan 31 06:48:16 EST 2024
Wed Jan 31 06:38:23 EST 2024
IsDoiOpenAccess false
IsOpenAccess true
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MeetingName DATE05: Design, Automation and Test in Europe
MergedId FETCHMERGED-LOGICAL-a307t-8889e33f2032d35dfd25ab722e5e57aa5b1bf963bac3a41cff407d9f3d8caba13
Notes SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
OpenAccessLink http://infoscience.epfl.ch/record/53050
PQID 31080026
PQPubID 23500
PageCount 6
ParticipantIDs proquest_miscellaneous_31080026
acm_books_10_1109_DATE_2005_5
ieee_primary_1395564
acm_books_10_1109_DATE_2005_5_brief
PublicationCentury 2000
PublicationDate 20050307
20050000
PublicationDateYYYYMMDD 2005-03-07
2005-01-01
PublicationDate_xml – month: 03
  year: 2005
  text: 20050307
  day: 07
PublicationDecade 2000
PublicationPlace Washington, DC, USA
PublicationPlace_xml – name: Washington, DC, USA
PublicationSeriesTitle ACM Conferences
PublicationTitle Design, Automation and Test in Europe
PublicationTitleAbbrev DATE
PublicationYear 2005
Publisher IEEE Computer Society
IEEE
Publisher_xml – name: IEEE Computer Society
– name: IEEE
SSID ssj0000394167
ssj0005329
Score 1.9197358
Snippet Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing...
Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing...
SourceID proquest
ieee
acm
SourceType Aggregation Database
Publisher
StartPage 246
SubjectTerms Computer systems organization -- Architectures -- Other architectures -- Reconfigurable computing
Computer systems organization -- Architectures -- Other architectures -- Self-organizing autonomic computing
Concrete
Emulation
Field programmable gate arrays
Hardware -- Communication hardware, interfaces and storage -- Buses and high-speed links
Hardware -- Hardware validation -- Functional verification -- Simulation and emulation
Hardware -- Very large scale integration design -- Application-specific VLSI designs
Hardware design languages
Network topology
Network-on-a-chip
Networks -- Network protocols
Scalability
Silicon
Switches
Testing
Title A Complete Network-On-Chip Emulation Framework
URI https://ieeexplore.ieee.org/document/1395564
https://www.proquest.com/docview/31080026
WOSCitedRecordID wos000228086900045&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PT8IwFH5B4kEvKGBERZfo0cK2rnQ9EoV4MIQDJtyadm0jBwbhh3-_bbehicbE25Zly_K6t_e91_e9D-DBIvpUkSRGEY4kcpLGSCZSIZZQIimJQ5V4ovArnUzS-ZxNa_B44MJorX3zme65Q7-Xr1bZ3pXK-hatEDJIjuCI0kHB1TrUU0LMEk_qrto7sFcosw4dIhuyoyJlZxZuWExZTt6pznFJ3ItC1n8ezkZFqcWFG5EtS9mVH_9qH4DGjf-9-hm0v5h8wfQQo86hpvMmNCoph6D07CacfptL2ILeMPCt5hZQB3nRJ45WOcreF-tAL0vBr8BUfV1teBuPZk8vqBRWQMK69A7ZrJdpjI1TT1eYKKNiIiSNY000oUIQGUljPVOKDIskyoyxaZ9iBqs0E1JE-ALq-SrXlxDElKU6UUQai_0MxSJ1T7UYQaVGSRl3oGttyF3GsOU-4QgZdzZ2-peEkw7c_3mdy81Cmw60nEn5upjAwUtrduCuWhNuvcJtdYhcr_ZbjiOPhAdXv994DSd-BKsvpdxAfbfZ6y4cZx-7xXZz6z-sTziMw3Q
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3fS8MwED50CuqLPzZx6lxBH83WNoltHkUninPsYcLeQtIkuId1sh_-_SZpOwVF8K2ltJRLr_fd5b77AK4sok8VJTGKcCSRkzRGkkiFGEmoTGgcKuKJwv1kMEjHYzbcgOs1F0Zr7ZvPdMcd-r18NctWrlTWtWiF0huyCVuUkDgs2FrrikqIGfG07qrBA3uNMuvSIbJBOyqSdmYBh0WV5eyd6hyX1L0oZN3721GvKLa4gCOyaSm88uNv7UPQw_7_Xv4AGl9cvmC4jlKHsKHzI9ivxByC0rePYO_bZMI6dG4D32xuIXWQF53iaJaj7G3yHuhpKfkVmKqzqwGvD73R3SMqpRWQsE69RDbvZRpj4_TTFabKqJgKmcSxppomQlAZSWN9U4oMCxJlxtjETzGDVZoJKSJ8DLV8lusTCOKEpZooKo1FfybBInVPtShBpUZJGTehZW3IXc6w4D7lCBl3NnYKmJTTJlz-eZ3L-USbJtSdSfl7MYODl9ZsQrtaE279wm12iFzPVguOI4-Fb05_v7ENO4-jlz7vPw2ez2DXD2T1hZVzqC3nK92C7exjOVnML_xH9gmV1ca7
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+the+conference+on+Design%2C+Automation+and+Test+in+Europe+-+Volume+1&rft.atitle=A+Complete+Network-On-Chip+Emulation+Framework&rft.au=Genko%2C+N.&rft.au=Atienza%2C+D.&rft.au=Micheli%2C+G.+De&rft.au=Mendias%2C+J.+M.&rft.series=ACM+Conferences&rft.date=2005-03-07&rft.pub=IEEE+Computer+Society&rft.isbn=9780769522883&rft.spage=246&rft.epage=251&rft_id=info:doi/10.1109%2FDATE.2005.5
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1530-1591&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1530-1591&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1530-1591&client=summon