Functional vector generation for HDL models using linear programming and 3-satisfiability

Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the HDL model, the search for input stimuli that...

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Bibliographic Details
Published in:DAC 98: DAC: 35th Annual ACM/IEEE Design Automation Conference pp. 528 - 533
Main Authors: Fallah, Farzan, Devadas, Srinivas, Keutzer, Kurt
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 01.01.1998
IEEE
Series:ACM Conferences
Subjects:
Applied computing > Physical sciences and engineering > Engineering
Arithmetic
Circuit simulation
Equations
Hardware > Electronic design automation > Hardware description languages and compilation
Hardware > Robustness
Hardware design languages
Integrated circuit interconnections
Linear programming
Logic programming
Mathematics of computing > Mathematical analysis > Mathematical optimization > Continuous optimization > Linear programming
Mathematics of computing > Mathematical software
Permission
Theory of computation > Design and analysis of algorithms > Mathematical optimization > Continuous optimization > Linear programming
Vectors
synthesis
codec
design automatian
level converters
voltage scaling
low power
placement
MPEG4
flip-flops
ISBN:0897919645, 9780897919647
Online Access:Get full text
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Summary:Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satisfiability checking problem by expanding the arithmetic modules into logic-gates. However, this approach is not very efficient. We present a new HDL-satisfiability checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of datapath modules, and 3-SAT checking for logic equations that govern the behavior of control modules. This feature is critically important to efficiency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-satisfiability checking algorithm in this paper. Experimental results which show significant speedups over state-of-the-art gate-level satisfiability checking methods are included.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0897919645
9780897919647
DOI:10.1145/277044.277187