Maze routing with buffer insertion and wiresizing

We propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing pr oblem as a graph-the oretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamic-programming based techniques. R outing c onstr aints suc...

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Vydáno v:37th Design Automation Conference, 2000 s. 374 - 378
Hlavní autoři: Lai, Minghorng, Wong, D. F.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 01.01.2000
IEEE
Edice:ACM Conferences
Témata:
Applied computing > Physical sciences and engineering > Engineering
Computer systems organization > Dependable and fault-tolerant systems and networks
Delay
Dynamic programming
General and reference > Cross-computing tools and techniques > Performance
Hardware > Electronic design automation > Physical design (EDA) > Placement
Hardware > Electronic design automation > Physical design (EDA) > Wire routing
Hardware > Robustness
Hardware > Very large scale integration design
Integrated circuit interconnections
Mathematics of computing > Discrete mathematics > Graph theory > Paths and connectivity problems
Networks > Network performance evaluation
Permission
Process design
Routing
Shortest path problem
Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Communications management > Buffering
Table lookup
Wires
Wiring
ISBN:9781581131871, 1581131879
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Shrnutí:We propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing pr oblem as a graph-the oretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamic-programming based techniques. R outing c onstr aints such as wiring obstacles and restrictions on buffer locations and types are easily inc orporated in the formulation. Furthermore, efficient softwar e routines solving shortest path problems in existing graph applic ation libraries can be applied. We construct a BP-Graph such that the length of every path in this graph is e qual to the Elmore delay. Therefore, finding the minimum Elmore delay path becomes a finite shortest path problem. The buffer choices and insertion locations are repr esente d as the vertices in the BP-Graph. The inter connect wir es are sized by constructing a look-up table for buffer-to-buffer wir esizing solutions. We also provide a technique that is able to tremendously improve the runtime. Experiments show improvements over previously proposed methods.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9781581131871
1581131879
DOI:10.1145/337292.337500