The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic

The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve integration density and clock speed values that are several orders of magnitude higher compared to current CMOS fabrication nodes. However, t...

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Vydáno v:Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference s. 576 - 581
Hlavní autoři: Drewniok, Jan, Walter, Marcel, Wille, Robert
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 22.01.2024
Témata:
Design automation
Fabrication
Layout
Libraries
Logic gates
Runtime
Silicon
ISSN:2153-697X
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Shrnutí:The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve integration density and clock speed values that are several orders of magnitude higher compared to current CMOS fabrication nodes. However, the exact physical simulation of SiDB layouts, which is an essential component of any design validation workflow, is computationally expensive. In this paper, we propose a novel algorithm called QuickExact, which aims to be both, efficient and exact. To this end, we are introducing three techniques, namely 1) Physically-informed Search Space Pruning, 2) Partial Solution Caching, and 3) Effective State Enumeration. Extensive experimental evaluations confirm that, compared to the state-of-the-art algorithm, the resulting approach leads to a paramount runtime advantage of more than a factor of 5000 on randomly generated layouts and more than a factor of 2000 on an established gate library.
ISSN:2153-697X
DOI:10.1109/ASP-DAC58780.2024.10473946