A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides
Detailed routing is a crucial and time-consuming stage for ASIC design. As the number and complexity of design rules increase, it is challenging to achieve high solution quality and fast speed at the same time in detailed routing. In this work, a high performance detailed routing algorithm named IPA...
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| Published in: | Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference pp. 975 - 980 |
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| Main Authors: | , , , , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
22.01.2024
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| ISSN: | 2153-697X |
| Online Access: | Get full text |
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| Abstract | Detailed routing is a crucial and time-consuming stage for ASIC design. As the number and complexity of design rules increase, it is challenging to achieve high solution quality and fast speed at the same time in detailed routing. In this work, a high performance detailed routing algorithm named IPAG with integer programming (IP) is proposed. The IP formulation uses the selection of candidate routes as decision variables. High quality candidate routes are generated by queue-based rip-up and reroute with adaptive global route guidance. A design rule checking engine which can simultaneously process nets with multiple routes is designed, to efficiently construct penalty parameters in the IP formulation. Experimental results on ISPD 2018 detailed routing benchmark show that IPAG achieves better solution quality in shorter or comparable runtime, as compared to the state-of-the-art academic detailed router. |
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| AbstractList | Detailed routing is a crucial and time-consuming stage for ASIC design. As the number and complexity of design rules increase, it is challenging to achieve high solution quality and fast speed at the same time in detailed routing. In this work, a high performance detailed routing algorithm named IPAG with integer programming (IP) is proposed. The IP formulation uses the selection of candidate routes as decision variables. High quality candidate routes are generated by queue-based rip-up and reroute with adaptive global route guidance. A design rule checking engine which can simultaneously process nets with multiple routes is designed, to efficiently construct penalty parameters in the IP formulation. Experimental results on ISPD 2018 detailed routing benchmark show that IPAG achieves better solution quality in shorter or comparable runtime, as compared to the state-of-the-art academic detailed router. |
| Author | Qi, Zhongdong Peng, Qi Han, Chao Hu, Shizhe Zhu, Zhangming You, Hailong |
| Author_xml | – sequence: 1 givenname: Zhongdong surname: Qi fullname: Qi, Zhongdong email: zdqi@xidian.edu.cn organization: Xidian University,School of Microelectronics – sequence: 2 givenname: Shizhe surname: Hu fullname: Hu, Shizhe organization: Xidian University,School of Microelectronics – sequence: 3 givenname: Qi surname: Peng fullname: Peng, Qi organization: Xidian University,School of Microelectronics – sequence: 4 givenname: Hailong surname: You fullname: You, Hailong organization: Xidian University,School of Microelectronics – sequence: 5 givenname: Chao surname: Han fullname: Han, Chao organization: Xidian University,School of Microelectronics – sequence: 6 givenname: Zhangming surname: Zhu fullname: Zhu, Zhangming organization: Xidian University,School of Microelectronics |
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| Snippet | Detailed routing is a crucial and time-consuming stage for ASIC design. As the number and complexity of design rules increase, it is challenging to achieve... |
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| SubjectTerms | Adaptive systems Benchmark testing Design automation Integer programming Navigation Routing Runtime |
| Title | A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides |
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