A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design

Path planning is a critical task in autonomous driving systems that is most susceptible to real-time constraints but often demands computationally intensive mathematical solvers, two contradictory goals. This conflict makes the computing of path planning a paramount challenge. At the heart of most p...

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Vydané v:Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 1 - 9
Hlavní autori: Zhang, Yanjun, Niu, Xiaoyu, Zhang, Yifan, Tian, Hongzheng, Yu, Bo, Liu, Shaoshan, Huang, Sitao
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Jazyk:English
Vydavateľské údaje: ACM 27.10.2024
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ISSN:1558-2434
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Abstract Path planning is a critical task in autonomous driving systems that is most susceptible to real-time constraints but often demands computationally intensive mathematical solvers, two contradictory goals. This conflict makes the computing of path planning a paramount challenge. At the heart of most path planners is the quadratic programming (QP) solver, which places excessive demands on the CPU in real-world autonomous driving applications. In this paper, we present an FPGA-based acceleration framework for path planning problems. Our approach leverages an operator splitting solver for quadratic programs (OSQP) and employs the preconditioned conjugate gradient (PCG) method for solving linear systems, which are customized to be more hardware-friendly than prior works. Specific memory management and parallel processing were tailored to the matrix pattern, and the incorporation of pipelining was executed to enhance throughput and execution speed. Our FPGA-based implementation achieves state-of-the-art performance against existing works, including an average 1.98 \times speedup compared with the state-of-the-art QP solver on Intel i7-11800H CPU, 3.90 \times speedup over an ARM Cortex-A57 embedded CPU, and 12.3 \times speedup over an NVIDIA RTX 3090 GPU.
AbstractList Path planning is a critical task in autonomous driving systems that is most susceptible to real-time constraints but often demands computationally intensive mathematical solvers, two contradictory goals. This conflict makes the computing of path planning a paramount challenge. At the heart of most path planners is the quadratic programming (QP) solver, which places excessive demands on the CPU in real-world autonomous driving applications. In this paper, we present an FPGA-based acceleration framework for path planning problems. Our approach leverages an operator splitting solver for quadratic programs (OSQP) and employs the preconditioned conjugate gradient (PCG) method for solving linear systems, which are customized to be more hardware-friendly than prior works. Specific memory management and parallel processing were tailored to the matrix pattern, and the incorporation of pipelining was executed to enhance throughput and execution speed. Our FPGA-based implementation achieves state-of-the-art performance against existing works, including an average 1.98 \times speedup compared with the state-of-the-art QP solver on Intel i7-11800H CPU, 3.90 \times speedup over an ARM Cortex-A57 embedded CPU, and 12.3 \times speedup over an NVIDIA RTX 3090 GPU.
Author Zhang, Yanjun
Tian, Hongzheng
Zhang, Yifan
Niu, Xiaoyu
Liu, Shaoshan
Yu, Bo
Huang, Sitao
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  organization: Beijing Institute of Technology
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  organization: Shenzhen Institute of Artificial Intelligence and Robotics for Society
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  organization: Shenzhen Institute of Artificial Intelligence and Robotics for Society
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  givenname: Sitao
  surname: Huang
  fullname: Huang, Sitao
  organization: University of California,Irvine
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Snippet Path planning is a critical task in autonomous driving systems that is most susceptible to real-time constraints but often demands computationally intensive...
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SubjectTerms autonomous driving
Autonomous vehicles
FPGA
Graphics processing units
Linear systems
Memory management
Path planning
Phonocardiography
Pipeline processing
Quadratic programming
Real-time systems
Throughput
Title A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design
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