SeGen: Automatic Topology Generator for Sequencing Elements
Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous sequencing-element proposals in the past, they have heavily relied on the expertise of designers, and their design method could not search all a...
Uložené v:
| Vydané v: | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design s. 1 - 9 |
|---|---|
| Hlavní autori: | , |
| Médium: | Konferenčný príspevok.. |
| Jazyk: | English |
| Vydavateľské údaje: |
ACM
27.10.2024
|
| Predmet: | |
| ISSN: | 1558-2434 |
| On-line prístup: | Získať plný text |
| Tagy: |
Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
|
| Abstract | Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous sequencing-element proposals in the past, they have heavily relied on the expertise of designers, and their design method could not search all available FF topologies. This paper introduces a design framework for automatically generating sequencing element designs, named SeGen. Motivated by the fact that the operation of all digital circuits can be represented by a Boolean function, we present SeGen which initially generates all possible Boolean functions for sequencing elements and derives circuit topologies from each of them. By adjusting the functionality qualification step of Boolean functions, SeGen can generate other sequencing elements such as toggle FFs and dual-edge-triggered FFs as well. A total of 40 resulting topologies newly generated by SeGen encompass the entire spectrum of positive-edge-triggered FFs, including master-slave FFs and pulsed latches, and consequentially provide a range of designs suitable for diverse applications. Several generated FFs such as SeGen8 and SeGen28 outperform recent human-crafted FFs and exhibit energy-delay product (EDP) improvement of 203%-257% at 1V supply voltage, compared to conventional transmission-gate FF (TGFF). |
|---|---|
| AbstractList | Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous sequencing-element proposals in the past, they have heavily relied on the expertise of designers, and their design method could not search all available FF topologies. This paper introduces a design framework for automatically generating sequencing element designs, named SeGen. Motivated by the fact that the operation of all digital circuits can be represented by a Boolean function, we present SeGen which initially generates all possible Boolean functions for sequencing elements and derives circuit topologies from each of them. By adjusting the functionality qualification step of Boolean functions, SeGen can generate other sequencing elements such as toggle FFs and dual-edge-triggered FFs as well. A total of 40 resulting topologies newly generated by SeGen encompass the entire spectrum of positive-edge-triggered FFs, including master-slave FFs and pulsed latches, and consequentially provide a range of designs suitable for diverse applications. Several generated FFs such as SeGen8 and SeGen28 outperform recent human-crafted FFs and exhibit energy-delay product (EDP) improvement of 203%-257% at 1V supply voltage, compared to conventional transmission-gate FF (TGFF). |
| Author | Jung, Wanyeong Kang, Kyounghun |
| Author_xml | – sequence: 1 givenname: Kyounghun surname: Kang fullname: Kang, Kyounghun email: rudgns546@kaist.ac.kr organization: Korea Advanced Institute of Science and Technology, School of Electrical Engineering,Daejeon,South Korea – sequence: 2 givenname: Wanyeong surname: Jung fullname: Jung, Wanyeong email: wanyeong@kaist.ac.kr organization: Korea Advanced Institute of Science and Technology, School of Electrical Engineering,Daejeon,South Korea |
| BookMark | eNotzM1Kw0AUBeBRFGxr1m5c5AVS52b-dVVKrYWCi9Z1mYn3lkAyU5N00bc3UheHDw6HM2V3MUVk7An4HECqF6GNVkLP_9Ra3bDMGWcl5wa4MeKWTUApW5RSyAeW9X0duOZqHEg7YW87XGN8zRfnIbV-qKt8n06pScdLPvbY-SF1OY3Z4c8ZY1XHY75qsMU49I_snnzTY_bvjH29r_bLj2L7ud4sF9vClw6GIgiyJAUnjmTIcTIOPanq23kbsPIKSYMa0d4rU5KWQODQBBeC4laIGXu-_taIeDh1deu7ywEASg2Oi1-lyUq6 |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1145/3676536.3676665 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE/IET Electronic Library (IEL) (UW System Shared) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISBN | 9798400710773 |
| EISSN | 1558-2434 |
| EndPage | 9 |
| ExternalDocumentID | 11126190 |
| Genre | orig-research |
| GrantInformation_xml | – fundername: Samsung Electronics Co., Ltd grantid: MEM230315_0004 funderid: 10.13039/100004358 – fundername: MSIT grantid: 2020-0-01297 funderid: 10.13039/501100009494 – fundername: IC Design Education Center funderid: 10.13039/501100003836 |
| GroupedDBID | 6IE 6IF 6IH 6IL 6IN AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO FEDTE IEGSK IJVOP OCL RIE RIL RIO |
| ID | FETCH-LOGICAL-a291t-b3f8f430f0ef7f90f79eaf5cd9a8beca5ef615a5e6aa572f641f19e7b9bb50833 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 0 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001479882200161&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Sep 03 07:09:38 EDT 2025 |
| IsDoiOpenAccess | false |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a291t-b3f8f430f0ef7f90f79eaf5cd9a8beca5ef615a5e6aa572f641f19e7b9bb50833 |
| OpenAccessLink | https://dl.acm.org/doi/pdf/10.1145/3676536.3676665 |
| PageCount | 9 |
| ParticipantIDs | ieee_primary_11126190 |
| PublicationCentury | 2000 |
| PublicationDate | 2024-Oct.-27 |
| PublicationDateYYYYMMDD | 2024-10-27 |
| PublicationDate_xml | – month: 10 year: 2024 text: 2024-Oct.-27 day: 27 |
| PublicationDecade | 2020 |
| PublicationTitle | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design |
| PublicationTitleAbbrev | ICCAD |
| PublicationYear | 2024 |
| Publisher | ACM |
| Publisher_xml | – name: ACM |
| SSID | ssib060584048 ssj0020286 |
| Score | 1.9047313 |
| Snippet | Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | automatic topology generation Boolean functions Digital integrated circuits energy efficiency finite-state machine Flip-flop Flip-flops Latches Main-secondary pulsed latch Qualifications Sequential analysis Simulation Topology Voltage |
| Title | SeGen: Automatic Topology Generator for Sequencing Elements |
| URI | https://ieeexplore.ieee.org/document/11126190 |
| WOSCitedRecordID | wos001479882200161&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NS8NAEB1s8aAXvyp-swevaZNmP7J6Emn1IKXQCr2V3WQGvKTSJoL_3t1NW3vx4GlDIBBmksy-zLz3AO5JYCILwgjJOoBC7pWy3t9EUyZiqynWRXAteVOjUTab6fGarB64MIgYhs-w6w9DL79Y5LX_VdZLPN_FVbAWtJSSDVlr8_D49h6P-baF4EB9JtdaPgkXPa9MJlLZ9av0pWTHTCXUkuHRP-_iGDq_rDw23tabE9jD8hQOdwQFz-Bxgi9YPrCnuloELVY2bUwQvlmjL-0QNnPbVDZpJqjdRWzQDJCvOvA-HEyfX6O1PUJk-jqpIptSRjyNKUZSpGNSGg2JvNAmc5kxAsltV9wijRGqT5InlGhUVlvrReDTc2iXixIvgLnsGDIOuWhE7iBHJkUh_PwEpcLKIr-Ejo_D_LNRwJhvQnD1x_lrOHDx5_4b31c30K6WNd7Cfv5VfayWdyFvP81ymK4 |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NS8NAEB20CurFr4rf7sFr2nzsbrJ6EmmtWEuhFXoru8kM9JJKmwr-e3eTtvbiwdMugcCyk2T2Zea9B3BPAgOZEXpIxgIUsq-Ucf4mihLhG0W-ykrXkm7c6yWjkeovyeolFwYRy-YzbLhpWcvPpunC_SprBo7vYjPYNuwIzkO_omutHh9X4OM-XxcRLKxP5FLNJ-Ci6bTJRCQbbpQumWzYqZTZpH34z3UcQf2Xl8f664xzDFuYn8DBhqTgKTwO8AXzB_a0KKalGisbVjYI36xSmLYYm9mDKhtUPdT2JtaqWsjndfhot4bPHW9pkODpUAWFZyJKiEc--UgxKZ9ihZpEmimd2NhogWQPLHaQWos4JMkDChTGRhnjZOCjM6jl0xzPgdn4aNIWuyhEbkFHIkUmXAcFRcLILL2AutuH8WelgTFebcHlH9fvYK8zfO-Ou6-9tyvYt7Hg7osfxtdQK2YLvIHd9KuYzGe3ZQx_APEcm_U |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Digest+of+technical+papers+-+IEEE%2FACM+International+Conference+on+Computer-Aided+Design&rft.atitle=SeGen%3A+Automatic+Topology+Generator+for+Sequencing+Elements&rft.au=Kang%2C+Kyounghun&rft.au=Jung%2C+Wanyeong&rft.date=2024-10-27&rft.pub=ACM&rft.eissn=1558-2434&rft.spage=1&rft.epage=9&rft_id=info:doi/10.1145%2F3676536.3676665&rft.externalDocID=11126190 |