DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs

Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA for better pipelining performance. However, uniform memory partitioning not only suffers from a local minim...

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Bibliographic Details
Published in:	2023 60th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors:	Liu, Dajiang, Mou, Di, Zhu, Rong, Zhuang, Yan, Shang, Jiaxing, Zhong, Jiang, Yin, Shouyi
Format:	Conference Proceeding
Language:	English
Published:	IEEE 09.07.2023
Subjects:	Banking CGRA Data Reuse Design automation Energy efficiency FIFO Memory management Parallel Data Access Partitioning algorithms Registers Throughput
Online Access:	Get full text
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Summary:	Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA for better pipelining performance. However, uniform memory partitioning not only suffers from a local minimum, but also introduces non-negligible overhead for banking function, which may greatly degrade the performance of CGRA. To this end, this paper introduces non-uniform memory partitioning and proposes a data-reuse-friendly CGRA (DARIC). With well elaborated configurable bank groups cooperated with register chains, elastic FIFOs can be achieved for non-uniform memory partitioning. Based on the resource graph of DARIC, a mapping algorithm supporting path sharing is proposed. Finally, the experimental results show that DARIC can achieve 2.35 × throughput and 2.59 × energy efficiency while having even less area and power overhead, as compared to the state-of-the-art.
DOI:	10.1109/DAC56929.2023.10247862