DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs

Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA for better pipelining performance. However, uniform memory partitioning not only suffers from a local minim...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:2023 60th ACM/IEEE Design Automation Conference (DAC) S. 1 - 6
Hauptverfasser: Liu, Dajiang, Mou, Di, Zhu, Rong, Zhuang, Yan, Shang, Jiaxing, Zhong, Jiang, Yin, Shouyi
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 09.07.2023
Schlagworte:
Banking
CGRA
Data Reuse
Design automation
Energy efficiency
FIFO
Memory management
Parallel Data Access
Partitioning algorithms
Registers
Throughput
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Abstract Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA for better pipelining performance. However, uniform memory partitioning not only suffers from a local minimum, but also introduces non-negligible overhead for banking function, which may greatly degrade the performance of CGRA. To this end, this paper introduces non-uniform memory partitioning and proposes a data-reuse-friendly CGRA (DARIC). With well elaborated configurable bank groups cooperated with register chains, elastic FIFOs can be achieved for non-uniform memory partitioning. Based on the resource graph of DARIC, a mapping algorithm supporting path sharing is proposed. Finally, the experimental results show that DARIC can achieve 2.35 × throughput and 2.59 × energy efficiency while having even less area and power overhead, as compared to the state-of-the-art.
AbstractList Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA for better pipelining performance. However, uniform memory partitioning not only suffers from a local minimum, but also introduces non-negligible overhead for banking function, which may greatly degrade the performance of CGRA. To this end, this paper introduces non-uniform memory partitioning and proposes a data-reuse-friendly CGRA (DARIC). With well elaborated configurable bank groups cooperated with register chains, elastic FIFOs can be achieved for non-uniform memory partitioning. Based on the resource graph of DARIC, a mapping algorithm supporting path sharing is proposed. Finally, the experimental results show that DARIC can achieve 2.35 × throughput and 2.59 × energy efficiency while having even less area and power overhead, as compared to the state-of-the-art.
Author Zhu, Rong
Mou, Di
Shang, Jiaxing
Yin, Shouyi
Liu, Dajiang
Zhong, Jiang
Zhuang, Yan
Author_xml – sequence: 1
  givenname: Dajiang
  surname: Liu
  fullname: Liu, Dajiang
  email: liudj@cqu.edu.cn
  organization: Chongqing University,College of Computer Science,Chongqing,China,400044
– sequence: 2
  givenname: Di
  surname: Mou
  fullname: Mou, Di
  email: moudi@cqu.edu.cn
  organization: Chongqing University,College of Computer Science,Chongqing,China,400044
– sequence: 3
  givenname: Rong
  surname: Zhu
  fullname: Zhu, Rong
  email: zhurong@cqu.edu.cn
  organization: Chongqing University,College of Computer Science,Chongqing,China,400044
– sequence: 4
  givenname: Yan
  surname: Zhuang
  fullname: Zhuang, Yan
  email: zhuangyan@cqu.edu.cn
  organization: Chongqing University,College of Computer Science,Chongqing,China,400044
– sequence: 5
  givenname: Jiaxing
  surname: Shang
  fullname: Shang, Jiaxing
  email: shangjx@cqu.edu.cn
  organization: Chongqing University,College of Computer Science,Chongqing,China,400044
– sequence: 6
  givenname: Jiang
  surname: Zhong
  fullname: Zhong, Jiang
  email: zhongjiang@cqu.edu.cn
  organization: Chongqing University,College of Computer Science,Chongqing,China,400044
– sequence: 7
  givenname: Shouyi
  surname: Yin
  fullname: Yin, Shouyi
  email: yinsy@tsinghua.edu.cn
  organization: Tsinghua University,School of Integrated Circuits,Beijing,China,100084
BookMark eNo1j9FKwzAUhiMoqLNvIJIXaD05SdPEu9KuczCYFL0eaXMChdpJU4W9vcLc1X_z8fH99-x6Ok7E2JOATAiwz3VZ5dqizRBQZgJQFUbjFUtsYY3MQaJURtyyJMahAw25UaDVHdvVZbutXnjJa7c43tJ3pLSZB5r8eOLVpi15OM78zc1uHGk8U2XfU4z8Z3B8Pbq4DD1vts0-PrCb4MZIyf-u2Eezfq9e091-s63KXerQwpJ6D3-RPhQOwHtrghVIvrOIATuNJlfS-d5pIXpbIOREKhiljNSdDoGCXLHHs3cgosPXPHy6-XS4nJa_tzpMvQ
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/DAC56929.2023.10247862
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798350323481
EndPage 6
ExternalDocumentID 10247862
Genre orig-research
GrantInformation_xml – fundername: National Natural Science Foundation of China
  funderid: 10.13039/501100001809
– fundername: Research and Development
  funderid: 10.13039/100006190
GroupedDBID 6IE
6IH
ACM
ALMA_UNASSIGNED_HOLDINGS
CBEJK
RIE
RIO
ID FETCH-LOGICAL-a290t-dd0023df7a00dd98f912edb922f2b628543adca611c97205ee4f844836b6ffef3
IEDL.DBID RIE
ISICitedReferencesCount 3
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001073487300174&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:51:00 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a290t-dd0023df7a00dd98f912edb922f2b628543adca611c97205ee4f844836b6ffef3
PageCount 6
ParticipantIDs ieee_primary_10247862
PublicationCentury 2000
PublicationDate 2023-July-9
PublicationDateYYYYMMDD 2023-07-09
PublicationDate_xml – month: 07
  year: 2023
  text: 2023-July-9
  day: 09
PublicationDecade 2020
PublicationTitle 2023 60th ACM/IEEE Design Automation Conference (DAC)
PublicationTitleAbbrev DAC
PublicationYear 2023
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssib060584064
Score 2.2457843
Snippet Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Banking
CGRA
Data Reuse
Design automation
Energy efficiency
FIFO
Memory management
Parallel Data Access
Partitioning algorithms
Registers
Throughput
Title DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
URI https://ieeexplore.ieee.org/document/10247862
WOSCitedRecordID wos001073487300174&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwGA06PHhScaJOJQevnU2btYm30q06kDmGwm4j7fcFBmOTrRv43_sl2xQPHryFkBB4-fG-_Hh5jN3LShLJSkWRG5SBFFUZKIjDwETCqJJIwxrwZhPpYKDGYz3cidW9FgYR_eMzbLukv8uHRbV2R2U0wyOZKrfiHqZpshVr7QePu94jcpI7FbAI9UM3yzsJ0X_bWYS395V_2ah4FilO_tn-KWv-6PH48JtpztgBzs_ZSzcb9fNHnvGuqQ0f4XqFQeG-LYbZJ8-fRhmngJQPzdLZpcy2pTLvj8g3U8N7FDfTqOFFv3hdNdl70XvLn4OdNwKhqMM6AHBsCzY1YQigldUiQig1gRuVXhYZG6hMIkSl0yjsIEqraCsWJ2ViLdr4gjXmizleMg7KVCbsWEAK3xRK6qE0ARQiKZF2U3DFmg6Kycf2-4vJHoXrP_Jb7NgB7t-06hvWqJdrvGVH1aaerpZ3vtO-AEFIlZE
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwGA0yBT2pOPG3OXjtTNq0TbyVbnXDOceYsNtI-32Fwdhk6wb-9ybZpnjw4C2UBMpL0vfS5OUR8iAKYUhWSKPcIPcEL3JPQsA87XMtc0MapQYXNhH3enI0Uv2tWd15YRDRHT7Dhi26vXyYFyv7q8zMcF_E0n5x90MhfLaxa-2Gj93gM_Qktj5gztRjM0nDyAiAhg0Jb-ya_wpScTySHf_zDU5I_ceRR_vfXHNK9nB2RrrNZNBJn2hCm7rSdICrJXqZvbgYpp80fR4k1EhS2tcLG5gy3dRKXEIiXU80bRnlbMYNzTrZ27JO3rPWMG1723QEg6NilQdg-RbKWDMGoGSpuI-QKwOvnztjZKCh0BHnhYp9FiKKUprFWBDlUVliGZyT2mw-wwtCQepCs7AENAJOojB9FEeAnEc5mvUUXJK6hWL8sbkAY7xD4eqP5_fksD187Y67nd7LNTmy4LsTruqG1KrFCm_JQbGuJsvFnevALz1HmNg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2023+60th+ACM%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=DARIC%3A+A+Data+Reuse-Friendly+CGRA+for+Parallel+Data+Access+via+Elastic+FIFOs&rft.au=Liu%2C+Dajiang&rft.au=Mou%2C+Di&rft.au=Zhu%2C+Rong&rft.au=Zhuang%2C+Yan&rft.date=2023-07-09&rft.pub=IEEE&rft.spage=1&rft.epage=6&rft_id=info:doi/10.1109%2FDAC56929.2023.10247862&rft.externalDocID=10247862