Formal Verification of Restoring Dividers made Fast and Simple

The paper describes a formal verification method for hardware implementation of restoring divider circuits. The method is based on setting select signals to predefined constants to reduce the design to easily verifiable circuit components, followed by their verification using standard equivalence ch...

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Vydané v:	2023 60th ACM/IEEE Design Automation Conference (DAC) s. 1 - 6
Hlavní autori:	Dasari, Jiteshri, Ciesielski, Maciej
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 09.07.2023
Predmet:	Computer bugs Debugging Design automation Formal verification Hardware Reverse engineering
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