An FPGA-Compatible TRNG with Ultra-High Throughput and Energy Efficiency

In this paper, we design an energy-efficient true random number generator with ultra-high throughput for FPGA. Only four ring oscillators constructed using eight LUTs are sampled by multiple sampling points to fully exploit the randomness of the entropy source, which provides high-quality and over 2...

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Published in:2023 60th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Lu, Zhaojun, Qidiao, Houjia, Chen, Qidong, Liu, Zhenglin, Zhang, Jiliang
Format: Conference Proceeding
Language:English
Published: IEEE 09.07.2023
Subjects:
Energy efficiency
Entropy
FPGA
NIST
ring oscillator
Routing
Source coding
Table lookup
Throughput
True random number generator
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Abstract In this paper, we design an energy-efficient true random number generator with ultra-high throughput for FPGA. Only four ring oscillators constructed using eight LUTs are sampled by multiple sampling points to fully exploit the randomness of the entropy source, which provides high-quality and over 275 Mbps random sequences while consuming 13 slices. An end-to-end implementation and testing framework is tailored for easy deployment and portability on Xilinx 7 serials FPGAs. The proposed architecture passes the NIST SP 800-22 and 800-90B tests without post-processing and outperforms the state-of-the-art in terms of minimum entropy and energy efficiency.
AbstractList In this paper, we design an energy-efficient true random number generator with ultra-high throughput for FPGA. Only four ring oscillators constructed using eight LUTs are sampled by multiple sampling points to fully exploit the randomness of the entropy source, which provides high-quality and over 275 Mbps random sequences while consuming 13 slices. An end-to-end implementation and testing framework is tailored for easy deployment and portability on Xilinx 7 serials FPGAs. The proposed architecture passes the NIST SP 800-22 and 800-90B tests without post-processing and outperforms the state-of-the-art in terms of minimum entropy and energy efficiency.
Author Lu, Zhaojun
Liu, Zhenglin
Qidiao, Houjia
Zhang, Jiliang
Chen, Qidong
Author_xml – sequence: 1
  givenname: Zhaojun
  surname: Lu
  fullname: Lu, Zhaojun
  organization: Huazhong University of Science and Technology,School of Cyber Science and Engineering
– sequence: 2
  givenname: Houjia
  surname: Qidiao
  fullname: Qidiao, Houjia
  organization: Huazhong University of Science and Technology,School of Cyber Science and Engineering
– sequence: 3
  givenname: Qidong
  surname: Chen
  fullname: Chen, Qidong
  organization: Huazhong University of Science and Technology,School of Cyber Science and Engineering
– sequence: 4
  givenname: Zhenglin
  surname: Liu
  fullname: Liu, Zhenglin
  organization: Huazhong University of Science and Technology,School of Cyber Science and Engineering
– sequence: 5
  givenname: Jiliang
  surname: Zhang
  fullname: Zhang, Jiliang
  email: zhangjiliang@hnu.edu.cn
  organization: Hunan University,College of Semiconductors (College of Integrated Circuits)
BookMark eNo1z9FKhEAUgOEJCqrNN4iYF9DGGR1nLsVcDZaKcK-XM3pGB1wVdQnfvou2q__ug_-R3A7jgIS8hCwIQ6Zf39IslprrgDMugpDxKEkieUM8nWglYia4iFR4T7xlcYZJFquIyeiBlOlA919F6mfjeYLVmR5p9f1R0B-3dvTYrzP4pWs7WnXzeGm76bJSGBqaDzi3G82tdbXDod6eyJ2FfkHv2h057vMqK_3DZ_GepQcfuGarr7jhsk6k0sIIBcYmsUpCrVEZUBZiKQBq2SBrpEUwkoEyEmodWR0Lgyh25PnPdYh4mmZ3hnk7_Q-LX4yhTbc
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/DAC56929.2023.10247746
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798350323481
EndPage 6
ExternalDocumentID 10247746
Genre orig-research
GrantInformation_xml – fundername: National Natural Science Foundation of China
  funderid: 10.13039/501100001809
GroupedDBID 6IE
6IH
ACM
ALMA_UNASSIGNED_HOLDINGS
CBEJK
RIE
RIO
ID FETCH-LOGICAL-a290t-82b26c76893b38abf7587199e8ba8fa563aac6de0d6feab60a8b6ac94f953bee3
IEDL.DBID RIE
ISICitedReferencesCount 17
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001073487300077&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:51:00 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a290t-82b26c76893b38abf7587199e8ba8fa563aac6de0d6feab60a8b6ac94f953bee3
PageCount 6
ParticipantIDs ieee_primary_10247746
PublicationCentury 2000
PublicationDate 2023-July-9
PublicationDateYYYYMMDD 2023-07-09
PublicationDate_xml – month: 07
  year: 2023
  text: 2023-July-9
  day: 09
PublicationDecade 2020
PublicationTitle 2023 60th ACM/IEEE Design Automation Conference (DAC)
PublicationTitleAbbrev DAC
PublicationYear 2023
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssib060584064
Score 2.3279066
Snippet In this paper, we design an energy-efficient true random number generator with ultra-high throughput for FPGA. Only four ring oscillators constructed using...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Energy efficiency
Entropy
FPGA
NIST
ring oscillator
Routing
Source coding
Table lookup
Throughput
True random number generator
Title An FPGA-Compatible TRNG with Ultra-High Throughput and Energy Efficiency
URI https://ieeexplore.ieee.org/document/10247746
WOSCitedRecordID wos001073487300077&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LawMhEJY29NBTW5rSNx56Nd1dH6vHkOZxCqEkkFsYdRYCYRPSTX9_1SQtPfTQmwgqjA7fOM7nR8iLcyXPc28ZV84zIaxiFiVnAawwhAcgwLskNlGOx3o-N5MDWT1xYRAxFZ9hJzbTW75fu11MlQUPL0QIV9QpOS1LtSdrHQ9PfN4L4CQOLOA8M69v3Z5UAf47USK8cxz8S0Ylocjg4p_rX5L2Dx-PTr6R5oqcYH1NRt2aDibDLksu3SztCun0fTykMbVKZ6tmCyxWcdDpXopns2so1J72E9uP9tPfEZF42SazQX_aG7GDLgKDwmQN04UtlAv3BMMt12CrEPOXuTGoLegKpOIATnnMvKoQrMpAWwXOiMpIbhH5DWnV6xpvCZUepPXa66ryIvdow6RliMqE804ajXekHc2w2Oy_vlgcLXD_R_8DOY_GTvWs5pG0mu0On8iZ-2yWH9vntGFfmRWXRw
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA5aBT2pWPFtDl5Td5tsNjmW2odYlyJb6K3kMQuFsi116-83SbeKBw_eQiAhTDLMl8l8-RB6NCalcWw1odxYwpjmRENCiQtW4OCBYsqaIDaRZpmYTuW4JqsHLgwAhOIzaPlmeMu3S7PxqTLn4W3m4ArfRwdeOquma-2Oj3_gc-GJ1TzgOJJPz51uwh0AaHmR8NZu-C8hlRBH-if_XMEpav4w8vD4O9acoT0oz9GwU-L-eNAhwamruV4Azt-zAfbJVTxZVGtFfB0HzrdiPKtNhVVpcS_w_XAv_B7hqZdNNOn38u6Q1MoIRLVlVBHR1m1u3E1BUk2F0oVD_WksJQitRKESTpUy3EJkeQFK80gJzZWRrJAJ1QD0AjXKZQmXCCdWJdoKK4rCstiCdpOmDpcxY00iBVyhpjfDbLX9_GK2s8D1H_0P6GiYv41mo5fs9QYde8OH6lZ5ixrVegN36NB8VvOP9X3YvC-sgZqQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2023+60th+ACM%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=An+FPGA-Compatible+TRNG+with+Ultra-High+Throughput+and+Energy+Efficiency&rft.au=Lu%2C+Zhaojun&rft.au=Qidiao%2C+Houjia&rft.au=Chen%2C+Qidong&rft.au=Liu%2C+Zhenglin&rft.date=2023-07-09&rft.pub=IEEE&rft.spage=1&rft.epage=6&rft_id=info:doi/10.1109%2FDAC56929.2023.10247746&rft.externalDocID=10247746