Optimal circuits for parallel bit reversal

In this paper, we develop novel parallel circuit designs for calculating the bit reversal. To perform bit reversal on 2 n data words, the designs take 2 k (k <; n) words as input each cycle. The circuits consist of concatenated single-port buffers and 2-to-1 multiplexers and use minimum number of...

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Bibliographic Details

Published in:	2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors:	Ren Chen, Prasanna, Viktor K.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.06.2017
Subjects:	Buffer storage Circuit synthesis Delays Hardware Memory management Ports (Computers) Switches
Online Access:	Get full text
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