Optimal circuits for parallel bit reversal - Ren Chen; Prasanna, Viktor K. (2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017)
In this paper, we develop novel parallel circuit designs for calculating the bit reversal. To perform bit reversal on 2 n data words, the designs take 2 k (k <; n) words as input each cycle. The circuits consist of concatenated single-port buffers and 2-to-1 multiplexers and use minimum number of registers for control. The designs consume minimum number of single-port memory banks that are necessary for calculating continuous-flow bit reversal, as well as near optimal 2 n memory words. The proposed parallel circuits can be built for any given fixed k and n , and achieve superior performance over state-of-the-art for calculating the bit reversal in parallel multi-path FFT architectures.