Optimal circuits for parallel bit reversal

In this paper, we develop novel parallel circuit designs for calculating the bit reversal. To perform bit reversal on 2 n data words, the designs take 2 k (k <; n) words as input each cycle. The circuits consist of concatenated single-port buffers and 2-to-1 multiplexers and use minimum number of...

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Bibliographic Details
Published in:2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Ren Chen, Prasanna, Viktor K.
Format: Conference Proceeding
Language:English
Published: IEEE 01.06.2017
Subjects:
Buffer storage
Circuit synthesis
Delays
Hardware
Memory management
Ports (Computers)
Switches
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Summary:In this paper, we develop novel parallel circuit designs for calculating the bit reversal. To perform bit reversal on 2 n data words, the designs take 2 k (k <; n) words as input each cycle. The circuits consist of concatenated single-port buffers and 2-to-1 multiplexers and use minimum number of registers for control. The designs consume minimum number of single-port memory banks that are necessary for calculating continuous-flow bit reversal, as well as near optimal 2 n memory words. The proposed parallel circuits can be built for any given fixed k and n , and achieve superior performance over state-of-the-art for calculating the bit reversal in parallel multi-path FFT architectures.
DOI:10.1145/3061639.3062295