APA (7th ed.) Citation

Chen, R., & Prasanna, V. K. (2017, June). Optimal circuits for parallel bit reversal. 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6. https://doi.org/10.1145/3061639.3062295

Chicago Style (17th ed.) Citation

Chen, Ren, and Viktor K. Prasanna. "Optimal Circuits for Parallel Bit Reversal." 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) Jun. 2017: 1-6. https://doi.org/10.1145/3061639.3062295.

MLA (9th ed.) Citation

Chen, Ren, and Viktor K. Prasanna. "Optimal Circuits for Parallel Bit Reversal." 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), Jun. 2017, pp. 1-6, https://doi.org/10.1145/3061639.3062295.