HLS-Based Optimization and Design Space Exploration for Applications with Variable Loop Bounds

In order to further increase the productivity of field-programmable gate array (FPGA) programmers, several design space exploration (DSE) frameworks for high-level synthesis (HLS) tools have been recently proposed to automatically determine the FPGA design parameters. However, one of the common limi...

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Bibliographic Details

Published in:	2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 1 - 8
Main Authors:	Choi, Young-kyu, Cong, Jason
Format:	Conference Proceeding
Language:	English
Published:	ACM 01.11.2018
Subjects:	Benchmark testing Field programmable gate arrays Optimization Pipeline processing Space exploration
ISSN:	1558-2434
Online Access:	Get full text
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