A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs

Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A d...

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Vydáno v:Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems s. 175 - 184
Hlavní autoři: Singh, Amit Kumar, Kumar, Akash, Srikanthan, Thambipillai
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 09.10.2011
IEEE
Edice:ACM Conferences
Témata:
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Bandwidth
Computer systems organization > Embedded and cyber-physical systems
Computer systems organization > Real-time systems
Decoding
design-time analysis
Multiprocessor
Optimization
run-time mapping
Synchronous Dataflow
Throughput
Tiles
Timing
run-time mapping
synchronous dataflow
multiprocessor
throughput
design-time analysis
ISBN:9781450307130, 1450307132
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Abstract Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at run-time subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the run-time mapping is speeded up by 93% when compared to state-of-the-art techniques.
AbstractList Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at runtime subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the runtime mapping is speeded up by 93% when compared to state-of-the-art techniques.
Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at run-time subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the run-time mapping is speeded up by 93% when compared to state-of-the-art techniques.
Author Kumar, Akash
Singh, Amit Kumar
Srikanthan, Thambipillai
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  email: astsrikan@ntu.edu.sg
  organization: Nanyang Technological University, Singapore, Singapore
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Keywords run-time mapping
synchronous dataflow
multiprocessor
throughput
design-time analysis
Language English
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Snippet Modern embedded systems are based on Multiprocessor-Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must...
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SubjectTerms Applied computing -- Arts and humanities -- Architecture (buildings) -- Computer-aided design
Applied computing -- Physical sciences and engineering -- Engineering -- Computer-aided design
Bandwidth
Computer systems organization -- Embedded and cyber-physical systems
Computer systems organization -- Real-time systems
Decoding
design-time analysis
Multiprocessor
Optimization
run-time mapping
Synchronous Dataflow
Throughput
Tiles
Timing
Title A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
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