Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber

Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies...

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Bibliographic Details
Published in:2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 1285 - 1290
Main Authors: Basso, Andrea, Roy, Sujoy Sinha
Format: Conference Proceeding
Language:English
Published: IEEE 05.12.2021
Subjects:
Computer architecture
Design automation
Hardware
NIST
Power demand
Standardization
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Summary:Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.
DOI:10.1109/DAC18074.2021.9586219