HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interfering with memory accesses. As DRAM chip density increases with technology node scaling, refresh operations also increase b...

Full description

Bibliographic Details

Published in:	2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 815 - 834
Main Authors:	Yaglikci, A. Giray, Olgun, Ataberk, Patel, Minesh, Luo, Haocong, Hassan, Hasan, Orosa, Lois, Ergin, Oguz, Mutlu, Onur
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.10.2022
Subjects:	Degradation DRAM DRAM chips Failure analysis memory access latency memory controller Microarchitecture Parallel processing refresh rowhammer Standards organizations System performance
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!