Local Bayesian Optimization For Analog Circuit Sizing

This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate Gaussian Process (GP) models approximating the objective and constraint functions locally in the search space. Unlike mainstream BO approaches, it i...

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Bibliographic Details
Published in:2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 1237 - 1242
Main Authors: Touloupas, Konstantinos, Chouridis, Nikos, Sotiriadis, Paul P.
Format: Conference Proceeding
Language:English
Published: IEEE 05.12.2021
Subjects:
Analog circuits
Bayes methods
Design automation
Focusing
Gaussian processes
Graphics processing units
Search problems
Online Access:Get full text
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Summary:This paper proposes a Bayesian Optimization (BO) algorithm to handle large-scale analog circuit sizing. The proposed approach uses a number of separate Gaussian Process (GP) models approximating the objective and constraint functions locally in the search space. Unlike mainstream BO approaches, it is able to traverse high dimensional problems with ease and provide multiple query points for parallel evaluation. To extend the method to large sample budgets, GP regression and sampling are enhanced by using kernel approximations and GPU acceleration. Experimental results demonstrate that the proposed method finds better solutions within given budgets of total evaluations compared to state-of-the-art approaches.
DOI:10.1109/DAC18074.2021.9586172