RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning

Gate sizing for timing optimization is performed extensively throughout electronic design automation (EDA) flows. However, increasing design sizes and time-to-market pressure force EDA tools to maintain pseudo-linear complexity, thereby limiting the global exploration done by the underlying sizing a...

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Bibliographic Details

Published in:	2021 58th ACM/IEEE Design Automation Conference (DAC) pp. 733 - 738
Main Authors:	Lu, Yi-Chen, Nath, Siddhartha, Khandelwal, Vishal, Lim, Sung Kyu
Format:	Conference Proceeding
Language:	English
Published:	IEEE 05.12.2021
Subjects:	Design automation Force Limiting Logic gates Reinforcement learning Very large scale integration
Online Access:	Get full text
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