PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning
In this work, we present a reinforcement learning (RL) based approach to designing parallel prefix circuits such as adders or priority encoders that are fundamental to high-performance digital design. Unlike prior methods, our approach designs solutions tabula rasa purely through learning with synth...
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| Vydané v: | 2021 58th ACM/IEEE Design Automation Conference (DAC) s. 853 - 858 |
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05.12.2021
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| Abstract | In this work, we present a reinforcement learning (RL) based approach to designing parallel prefix circuits such as adders or priority encoders that are fundamental to high-performance digital design. Unlike prior methods, our approach designs solutions tabula rasa purely through learning with synthesis in the loop. We design a grid-based state-action representation and an RL environment for constructing legal prefix circuits. Deep Convolutional RL agents trained on this environment produce prefix adder circuits that Pareto-dominate existing baselines with up to 16.0% and 30.2% lower area for the same delay in the 32b and 64b settings respectively. We observe that agents trained with open-source synthesis tools and cell library can design adder circuits that achieve lower area and delay than commercial tool adders in an industrial cell library. |
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| AbstractList | In this work, we present a reinforcement learning (RL) based approach to designing parallel prefix circuits such as adders or priority encoders that are fundamental to high-performance digital design. Unlike prior methods, our approach designs solutions tabula rasa purely through learning with synthesis in the loop. We design a grid-based state-action representation and an RL environment for constructing legal prefix circuits. Deep Convolutional RL agents trained on this environment produce prefix adder circuits that Pareto-dominate existing baselines with up to 16.0% and 30.2% lower area for the same delay in the 32b and 64b settings respectively. We observe that agents trained with open-source synthesis tools and cell library can design adder circuits that achieve lower area and delay than commercial tool adders in an industrial cell library. |
| Author | Raiman, Jonathan Oberman, Stuart Roy, Rajarshi Catanzaro, Bryan Godil, Saad Siu, Michael Kant, Neel Elkin, Ilyas Kirby, Robert |
| Author_xml | – sequence: 1 givenname: Rajarshi surname: Roy fullname: Roy, Rajarshi email: rajarshir@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 2 givenname: Jonathan surname: Raiman fullname: Raiman, Jonathan email: jraiman@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 3 givenname: Neel surname: Kant fullname: Kant, Neel email: nkant@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 4 givenname: Ilyas surname: Elkin fullname: Elkin, Ilyas email: ielkin@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 5 givenname: Robert surname: Kirby fullname: Kirby, Robert email: rkirby@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 6 givenname: Michael surname: Siu fullname: Siu, Michael email: msiu@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 7 givenname: Stuart surname: Oberman fullname: Oberman, Stuart email: soberman@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 8 givenname: Saad surname: Godil fullname: Godil, Saad email: sgodil@nvidia.com organization: NVIDIA,Santa Clara,CA,USA – sequence: 9 givenname: Bryan surname: Catanzaro fullname: Catanzaro, Bryan email: bcatanzaro@nvidia.com organization: NVIDIA,Santa Clara,CA,USA |
| BookMark | eNotj8tKw0AYhUdQUGueQIR5gca5X9yV1BsEWkpdl5nkHxlIJmGSgvr0FtrNOYvv8MG5R9dpSIDQEyUlpcQ-r1cVNUSLkhFGSyuNIlZcocJqQ5WSgjMtyC0qpil6oog04pR3aL_NEOLPrn7Bm3GOffxzcxwSHgLeuuy6Djp8nuAq5uYY5wkfp5i-8RpgxDuIKQy5gR7SjGtwOZ3YA7oJrpuguPQCfb297quPZb15_6xW9dIxo-elc5o76w2AbKz3IbS8FZxyCmC0U1waZmwrvfLSBKASmGWiNWCt19QSxhfo8eyNAHAYc-xd_j1cvvN_ePRShA |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1109/DAC18074.2021.9586094 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| EISBN | 9781665432740 1665432748 |
| EndPage | 858 |
| ExternalDocumentID | 9586094 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IH ACM ALMA_UNASSIGNED_HOLDINGS CBEJK RIE RIO |
| ID | FETCH-LOGICAL-a287t-aa73a9b8ee5c9bbffd3d43131ee87a6358289d5b6b58fe15e2924d8e99b719023 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 32 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000766079700143&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 02:28:30 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a287t-aa73a9b8ee5c9bbffd3d43131ee87a6358289d5b6b58fe15e2924d8e99b719023 |
| PageCount | 6 |
| ParticipantIDs | ieee_primary_9586094 |
| PublicationCentury | 2000 |
| PublicationDate | 2021-Dec.-5 |
| PublicationDateYYYYMMDD | 2021-12-05 |
| PublicationDate_xml | – month: 12 year: 2021 text: 2021-Dec.-5 day: 05 |
| PublicationDecade | 2020 |
| PublicationTitle | 2021 58th ACM/IEEE Design Automation Conference (DAC) |
| PublicationTitleAbbrev | DAC |
| PublicationYear | 2021 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssib060584060 |
| Score | 2.4378808 |
| Snippet | In this work, we present a reinforcement learning (RL) based approach to designing parallel prefix circuits such as adders or priority encoders that are... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 853 |
| SubjectTerms | datapath optimization Delays Libraries machine learning Machine learning algorithms Reinforcement learning Task analysis Training |
| Title | PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning |
| URI | https://ieeexplore.ieee.org/document/9586094 |
| WOSCitedRecordID | wos000766079700143&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEA1t8eBJpRW_ycGj226aZpN4k9biQepSKvRWkuykLGhbtrvizzdJ14rgxVsI-YBJwuQl894gdKssZ9oMdCSzxAEUyuNIE6OjRDs8pHWsNLUh2QSfTMR8LtMGuttzYQAgBJ9B1xfDX362NpV_KutJJhIHR5qoyXmy42p97x3_u-d8U1yTdEgse6OHIfFSLw4E9km37vsriUrwIeOj_81-jDo_ZDyc7t3MCWrAqo1mqfNs-ef0-R6_uEP_XrMp8driVBU-P8ob3jXBw7wwVV5usQ9xX-IRwAZPIQimmvA2iGuN1WUHvY4fZ8OnqE6QECkHdMpIKU6V1AKAGam1tRnN3IWAEgDBVeJJsEJmTCeaCQuEQd-hrUyAlJq7i0CfnqLWar2CM4QTbhW1SsaMmcHAjZaRGCin0uEPr2B4jtreIovNTgNjURvj4u_qS3TojR7CPtgVapVFBdfowHyU-ba4CQv3BYgumos |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwGA1zCnpS2cTf5uDRbu2yNIk32ZSJc5YxYbeRpF9GQbfRdeKfb5LVieDFWwhpAknDl5d87z2ErqVhVOm2CkQaW4BCWBioSKsgVhYPKRVKRYw3m2CDAR-PRVJBNxsuDAD45DNouKJ_y0_neuWuypqC8tjCkS207ZyzSrbW99_j3vdsdApLmk4Uimb3rhM5sRcLA1tRo_z6l42KjyIP-_8b_wDVf-h4ONkEmkNUgVkNjRIb27LPYf8Wv9ht_17yKfHc4ETmziHlDa-b4E6W61VWLLFLcp_iLsACD8FLpmp_O4hLldVpHb0-3I86vaC0SAikhTpFICUjUigOQLVQypiUpPZIQCIAzmTsaLBcpFTFinIDEYWWxVspByEUs0eBFjlC1dl8BscIx8xIYqQIKdXttu0tjUIgjAiLQJyG4QmquRmZLNYqGJNyMk7_rr5Cu73Rc3_Sfxw8naE9twA-CYSeo2qRr-AC7eiPIlvml34RvwDGQp3U |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2021+58th+ACM%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=PrefixRL%3A+Optimization+of+Parallel+Prefix+Circuits+using+Deep+Reinforcement+Learning&rft.au=Roy%2C+Rajarshi&rft.au=Raiman%2C+Jonathan&rft.au=Kant%2C+Neel&rft.au=Elkin%2C+Ilyas&rft.date=2021-12-05&rft.pub=IEEE&rft.spage=853&rft.epage=858&rft_id=info:doi/10.1109%2FDAC18074.2021.9586094&rft.externalDocID=9586094 |