An Automated and Process-Portable Generator for Phase-Locked Loop

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. T...

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Vydáno v:	2021 58th ACM/IEEE Design Automation Conference (DAC) s. 511 - 516
Hlavní autoři:	Wang, Zhongkai, Choi, Minsoo, Chang, Eric, Wright, John, Bae, Wooham, Du, Sijun, Liu, Zhaokai, Narevsky, Nathan, Schmidt, Colin, Biwas, Ayan, Nikolic, Borivoje, Alon, Elad
Médium:	Konferenční příspěvek
Jazyk:	angličtina
Vydáno:	IEEE 05.12.2021
Témata:	Automatic frequency control Berkeley Analog Generator Design automation Design methodology jitter Layout Phase noise phase-locked loop Semiconductor device measurement voltage-controlled oscillator Voltage-controlled oscillators
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Popis
Shrnutí:	We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.
DOI:	10.1109/DAC18074.2021.9586318