GPU-accelerated Path-based Timing Analysis

Path-based Analysis (PBA) is an important step in the design closure flow for reducing slack pessimism. However, PBA is extremely time-consuming. Recent years have seen many parallel PBA algorithms, but most of them are architecturally constrained by the CPU parallelism and do not scale beyond a few...

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Veröffentlicht in:2021 58th ACM/IEEE Design Automation Conference (DAC) S. 721 - 726
Hauptverfasser: Guo, Guannan, Huang, Tsung-Wei, Lin, Yibo, Wong, Martin
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 05.12.2021
Schlagworte:
Data structures
Graphics processing units
Instruction sets
Logic gates
Parallel processing
Runtime
Timing
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Abstract Path-based Analysis (PBA) is an important step in the design closure flow for reducing slack pessimism. However, PBA is extremely time-consuming. Recent years have seen many parallel PBA algorithms, but most of them are architecturally constrained by the CPU parallelism and do not scale beyond a few threads. To overcome this challenge, we propose in this paper a new fast and accurate PBA algorithm by harnessing the power of graphics processing unit (GPU). We introduce GPU-efficient data structures, high-performance kernels, and efficient CPU-GPU task decomposition strateiges, to accelerate PBA to a new performance milestone. Experimental results show that our method can speed up the state-of-the-art algorithm by 543\times on a design of 1.6 million gates with exact accuracy. At the extreme, our method of 1 CPU and 1 GPU outperforms the state-of-the-art algorithm of 40 CPUs by 25-45\times.
AbstractList Path-based Analysis (PBA) is an important step in the design closure flow for reducing slack pessimism. However, PBA is extremely time-consuming. Recent years have seen many parallel PBA algorithms, but most of them are architecturally constrained by the CPU parallelism and do not scale beyond a few threads. To overcome this challenge, we propose in this paper a new fast and accurate PBA algorithm by harnessing the power of graphics processing unit (GPU). We introduce GPU-efficient data structures, high-performance kernels, and efficient CPU-GPU task decomposition strateiges, to accelerate PBA to a new performance milestone. Experimental results show that our method can speed up the state-of-the-art algorithm by 543\times on a design of 1.6 million gates with exact accuracy. At the extreme, our method of 1 CPU and 1 GPU outperforms the state-of-the-art algorithm of 40 CPUs by 25-45\times.
Author Huang, Tsung-Wei
Guo, Guannan
Wong, Martin
Lin, Yibo
Author_xml – sequence: 1
  givenname: Guannan
  surname: Guo
  fullname: Guo, Guannan
  organization: University of Illinois at Urbana-Champaign,Department of Electrical and Computer Engineering,IL,USA
– sequence: 2
  givenname: Tsung-Wei
  surname: Huang
  fullname: Huang, Tsung-Wei
  organization: University of Utah,Department of Electrical and Computer Engineering,Salt Lake City,UT,USA
– sequence: 3
  givenname: Yibo
  surname: Lin
  fullname: Lin, Yibo
  organization: Peking University,Department of Computer Science,Beijing,China
– sequence: 4
  givenname: Martin
  surname: Wong
  fullname: Wong, Martin
  organization: University of Illinois at Urbana-Champaign,Department of Electrical and Computer Engineering,IL,USA
BookMark eNotj81Kw0AYRUewoLZ5AhG6FhLn_2cZoq1CwS7adflm5hsdSKNksunbG7Cbe8_qcu4DuR1-BiTkidGGMepeXtuOWWpkwylnjVNWC6ZvSOWMZVorKbiR9I5UpWRPNVVWznlPnrf7Yw0hYI8jTBjXe5i-aw9lxkM-5-Fr3Q7QX0ouK7JI0Besrr0kx83boXuvd5_bj67d1cCtmWqBIdggedI2Ss-dCMJb5Mkl60wAkxhI7ZWKiVoK0cfIGBeYZncDnmuxJI__uxkRT79jPsN4OV0fiT-88kLL
ContentType Conference Proceeding
DBID 6IE
6IH
CBEJK
RIE
RIO
DOI 10.1109/DAC18074.2021.9586316
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan (POP) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP) 1998-present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781665432740
1665432748
EndPage 726
ExternalDocumentID 9586316
Genre orig-research
GroupedDBID 6IE
6IH
ACM
ALMA_UNASSIGNED_HOLDINGS
CBEJK
RIE
RIO
ID FETCH-LOGICAL-a287t-3ecc8c42f68d4b293c3b8e2f9f897ca7f1a46b55df080adbdd1123ef0747ab263
IEDL.DBID RIE
ISICitedReferencesCount 23
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000766079700121&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:28:29 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a287t-3ecc8c42f68d4b293c3b8e2f9f897ca7f1a46b55df080adbdd1123ef0747ab263
PageCount 6
ParticipantIDs ieee_primary_9586316
PublicationCentury 2000
PublicationDate 2021-Dec.-5
PublicationDateYYYYMMDD 2021-12-05
PublicationDate_xml – month: 12
  year: 2021
  text: 2021-Dec.-5
  day: 05
PublicationDecade 2020
PublicationTitle 2021 58th ACM/IEEE Design Automation Conference (DAC)
PublicationTitleAbbrev DAC
PublicationYear 2021
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssib060584060
Score 2.3195329
Snippet Path-based Analysis (PBA) is an important step in the design closure flow for reducing slack pessimism. However, PBA is extremely time-consuming. Recent years...
SourceID ieee
SourceType Publisher
StartPage 721
SubjectTerms Data structures
Graphics processing units
Instruction sets
Logic gates
Parallel processing
Runtime
Timing
Title GPU-accelerated Path-based Timing Analysis
URI https://ieeexplore.ieee.org/document/9586316
WOSCitedRecordID wos000766079700121&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEJ4A8eBJDRjf2YMnY4Hdvo8GRU9kD5BwI32N8QIGF36_7bJgTLx4a5o2zfSRbzrt9w3AvdAKXe4FQRwGwuJZJLZIcSvGmdXaSUSsk03IyUTN57psweOBCxNCqD-fhX4q1m_5fuU2KVQ20FwJmos2tKUUO67Wfu-k172ITcOGpJMP9eD5aZQnqZd4CSzyftP3VxKVGkPGJ_8b_RR6P2S8rDzAzBm0wrILD6_ljBjnImgkrQefldGTIwmSfDZNibres73cSA9m45fp6I00aQ-IideXitA4q8qxAoXyzEY4dtSqUKBGpaUzEnPDhOXcY_T2jLfeR5-JBkxS-MYWgp5DZ7lahgvIFFIuGWrGvGEhGBMbFU54Q7kR1ohL6CY7F587ZYtFY-LV39XXcJymsv7MwW-gU6034RaO3Lb6-Frf1cvxDfxVi4M
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEJ4gmuhJDRjf7sGTsbDb17ZHgyJGJHuAhBvp03ABg-Dvt10WjIkXb03Tppk-8k2n_b4BuOVSeJNZjrxPHaLhLCKNY9yKMqqlNLn3vkw2kQ8GYjyWRQ3ut1wY51z5-cy1YrF8y7dzs4qhsrZkgpOM78AuoxSna7bWZvfE972ATmlF08lS2X586GRR7CVcA3HWqnr_SqNSokj38H_jH0Hzh46XFFugOYaamzXg7rkYIWVMgI2o9mCTIvhyKIKSTYYxVdd7shEcacKo-zTs9FCV-ACpcIFZIhLmVRiKPReW6gDIhmjhsJdeyNyo3GeKcs2Y9cHfU1ZbG7wm4nwUw1cac3IC9dl85k4hEZ6wnHpJqVXUOaVCI2y4VYQprhU_g0a0c_Kx1raYVCae_119A_u94Vt_0n8ZvF7AQZzW8msHu4T6crFyV7BnvpbTz8V1uTTfcmaOyg
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2021+58th+ACM%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=GPU-accelerated+Path-based+Timing+Analysis&rft.au=Guo%2C+Guannan&rft.au=Huang%2C+Tsung-Wei&rft.au=Lin%2C+Yibo&rft.au=Wong%2C+Martin&rft.date=2021-12-05&rft.pub=IEEE&rft.spage=721&rft.epage=726&rft_id=info:doi/10.1109%2FDAC18074.2021.9586316&rft.externalDocID=9586316