Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMR

DM-SMR adopts Persistent Cache (PC) to accommodate non-sequential write operations. However, the PC cleaning process induces severe long-tail latency. In this paper, we propose to mitigate the tail latency of PC cleaning by using Reinforcement Learning (RL). Specifically, a real-time lightweight Q-l...

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Veröffentlicht in:2021 58th ACM/IEEE Design Automation Conference (DAC) S. 103 - 108
Hauptverfasser: Pan, Yungang, Jia, Zhiping, Shen, Zhaoyan, Li, Bingzhe, Chang, Wanli, Shao, Zili
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 05.12.2021
Schlagworte:
Cleaning
Cleaning Process
Design automation
Idle Time Window
Linux
Real-time systems
Reinforcement learning
Shingled Magnetic Recording
Tail-Latency
Time factors
Timing
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Zusammenfassung:DM-SMR adopts Persistent Cache (PC) to accommodate non-sequential write operations. However, the PC cleaning process induces severe long-tail latency. In this paper, we propose to mitigate the tail latency of PC cleaning by using Reinforcement Learning (RL). Specifically, a real-time lightweight Q-learning model is built to analyze the idle window of I/O workloads, based on which PC cleaning is judiciously scheduled, thereby maximally utilizing the I/O idle window and effectively hiding the tail latency from regular requests. We implement our technique inside a Linux device driver with an emulated SMR drive. Experimental results show that our technique can reduce the tail latency by 57.65% at 99.9th percentile and the average response time by 46.11% compared to a typical SMR design.
DOI:10.1109/DAC18074.2021.9586084