Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMR
DM-SMR adopts Persistent Cache (PC) to accommodate non-sequential write operations. However, the PC cleaning process induces severe long-tail latency. In this paper, we propose to mitigate the tail latency of PC cleaning by using Reinforcement Learning (RL). Specifically, a real-time lightweight Q-l...
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| Vydáno v: | 2021 58th ACM/IEEE Design Automation Conference (DAC) s. 103 - 108 |
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05.12.2021
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| Abstract | DM-SMR adopts Persistent Cache (PC) to accommodate non-sequential write operations. However, the PC cleaning process induces severe long-tail latency. In this paper, we propose to mitigate the tail latency of PC cleaning by using Reinforcement Learning (RL). Specifically, a real-time lightweight Q-learning model is built to analyze the idle window of I/O workloads, based on which PC cleaning is judiciously scheduled, thereby maximally utilizing the I/O idle window and effectively hiding the tail latency from regular requests. We implement our technique inside a Linux device driver with an emulated SMR drive. Experimental results show that our technique can reduce the tail latency by 57.65% at 99.9th percentile and the average response time by 46.11% compared to a typical SMR design. |
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| AbstractList | DM-SMR adopts Persistent Cache (PC) to accommodate non-sequential write operations. However, the PC cleaning process induces severe long-tail latency. In this paper, we propose to mitigate the tail latency of PC cleaning by using Reinforcement Learning (RL). Specifically, a real-time lightweight Q-learning model is built to analyze the idle window of I/O workloads, based on which PC cleaning is judiciously scheduled, thereby maximally utilizing the I/O idle window and effectively hiding the tail latency from regular requests. We implement our technique inside a Linux device driver with an emulated SMR drive. Experimental results show that our technique can reduce the tail latency by 57.65% at 99.9th percentile and the average response time by 46.11% compared to a typical SMR design. |
| Author | Chang, Wanli Li, Bingzhe Shen, Zhaoyan Pan, Yungang Shao, Zili Jia, Zhiping |
| Author_xml | – sequence: 1 givenname: Yungang surname: Pan fullname: Pan, Yungang email: dlzrmr@mail.sdu.edu.cn organization: Shandong University,School of Computer Science and Technology,Qingdao,China – sequence: 2 givenname: Zhiping surname: Jia fullname: Jia, Zhiping email: jzp@sdu.edu.cn organization: Shandong University,School of Computer Science and Technology,Qingdao,China – sequence: 3 givenname: Zhaoyan surname: Shen fullname: Shen, Zhaoyan email: shenzhaoyan@sdu.edu.cn organization: Shandong University,School of Computer Science and Technology,Qingdao,China – sequence: 4 givenname: Bingzhe surname: Li fullname: Li, Bingzhe email: bingzhe.li@okstate.edu organization: Oklahoma State University,School of Electrical and Computer Engineering,Stillwater,OK,United States – sequence: 5 givenname: Wanli surname: Chang fullname: Chang, Wanli email: wanli.chang@york.ac.uk organization: Hunan University,College of Computer Science and Electronic Engineering,Changsha,China – sequence: 6 givenname: Zili surname: Shao fullname: Shao, Zili email: shao@cse.cuhk.edu.hk organization: The Chinese University of Hong Kong,Department of Computer Science and Engineering,Shatin,NT,Hong Kong |
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| Snippet | DM-SMR adopts Persistent Cache (PC) to accommodate non-sequential write operations. However, the PC cleaning process induces severe long-tail latency. In this... |
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| SubjectTerms | Cleaning Cleaning Process Design automation Idle Time Window Linux Real-time systems Reinforcement learning Shingled Magnetic Recording Tail-Latency Time factors Timing |
| Title | Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMR |
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