CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all the in-flight loads and is searched on every invalidation and cache eviction. Moreover, in a simultaneous multithreading processor (SMT), sto...

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Published in:2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) pp. 1 - 13
Main Authors: Singh, Sawan, Feliu, Josue, Acacio, Manuel E., Jimborean, Alexandra, Ros, Alberto
Format: Conference Proceeding
Language:English
Published: IEEE 21.10.2023
Subjects:
Computer languages
Energy consumption
Hardware
Multithreading
Out of order
Parallel architectures
Writing
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Abstract Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all the in-flight loads and is searched on every invalidation and cache eviction. Moreover, in a simultaneous multithreading processor (SMT), stores also search the LQ when writing to cache. LQ searches entail considerable energy consumption. Furthermore, the processor stalls upon encountering the LQ full or when its ports are busy. Hence, the LQ is a critical structure in terms of both energy and performance. In this work, we observe that the use of the LQ could be dramatically optimized under the guarantees of the datarace-free (DRF) property imposed by modern programming languages. To leverage this observation, we propose CELLO, a software-hardware co-design in which the compiler detects memory operations in DRF regions and the hardware optimizes their execution by safely skipping LQ searches without violating the TSO consistency model. Furthermore, CELLO allows removing DRF loads from the LQ earlier, as they do not need to be searched to detect consistency violations. With minimal hardware overhead, we show that an 8-core 2-way SMT processor with CELLO avoids almost all conservative searches to the LQ and significantly reduces its occupancy. CELLO allows i) to reduce the LQ energy expenditure by 33% on average (up to 53%) while performing 2.8% better on average (up to 18.6%) than the baseline system, and ii) to shrink the LQ size from 192 to only 80 entries, reducing the LQ energy expenditure as much as 69% while performing on par with a mainstream LQ implementation.
AbstractList Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all the in-flight loads and is searched on every invalidation and cache eviction. Moreover, in a simultaneous multithreading processor (SMT), stores also search the LQ when writing to cache. LQ searches entail considerable energy consumption. Furthermore, the processor stalls upon encountering the LQ full or when its ports are busy. Hence, the LQ is a critical structure in terms of both energy and performance. In this work, we observe that the use of the LQ could be dramatically optimized under the guarantees of the datarace-free (DRF) property imposed by modern programming languages. To leverage this observation, we propose CELLO, a software-hardware co-design in which the compiler detects memory operations in DRF regions and the hardware optimizes their execution by safely skipping LQ searches without violating the TSO consistency model. Furthermore, CELLO allows removing DRF loads from the LQ earlier, as they do not need to be searched to detect consistency violations. With minimal hardware overhead, we show that an 8-core 2-way SMT processor with CELLO avoids almost all conservative searches to the LQ and significantly reduces its occupancy. CELLO allows i) to reduce the LQ energy expenditure by 33% on average (up to 53%) while performing 2.8% better on average (up to 18.6%) than the baseline system, and ii) to shrink the LQ size from 192 to only 80 entries, reducing the LQ energy expenditure as much as 69% while performing on par with a mainstream LQ implementation.
Author Feliu, Josue
Acacio, Manuel E.
Ros, Alberto
Singh, Sawan
Jimborean, Alexandra
Author_xml – sequence: 1
  givenname: Sawan
  surname: Singh
  fullname: Singh, Sawan
  email: singh.sawan@um.es
  organization: University of Murcia,Computer Engineering Department,Murcia,Spain
– sequence: 2
  givenname: Josue
  surname: Feliu
  fullname: Feliu, Josue
  email: jfeliu@disca.upv.es
  organization: Universitat Politècnica de València,Computer Engineering Department,València,Spain
– sequence: 3
  givenname: Manuel E.
  surname: Acacio
  fullname: Acacio, Manuel E.
  email: meacacio@um.es
  organization: University of Murcia,Computer Engineering Department,Murcia,Spain
– sequence: 4
  givenname: Alexandra
  surname: Jimborean
  fullname: Jimborean, Alexandra
  email: alexandra.jimborean@um.es
  organization: University of Murcia,Computer Engineering Department,Murcia,Spain
– sequence: 5
  givenname: Alberto
  surname: Ros
  fullname: Ros, Alberto
  email: aros@ditec.um.es
  organization: University of Murcia,Computer Engineering Department,Murcia,Spain
BookMark eNotjFFLwzAUhSMoqLP_YA_5A5lJbrM0vo3aqVCojPk8bpLbEdjakfbFf-9Ez8P54PBxHtntMA7E2FLJlVLSPX9u6r2plLIrLTWs5DXuhhXOugqMhFKbEu5ZMU3JS2MtWO3ggXV107bdC6_H8yWdKIvNVZhmirzp-xQSDTNvR4zit3iXI-U0HHka-CvOKHYYSGwzEd_RMY3D9MTuejxNVPxzwb62zb5-F2339lFvWoG6Ws_Cq3WwMUQkcq6kErV30FvlbRVI-RKjgqBl9AZcNMZhf90CGtcbD5VHWLDl328iosMlpzPm74OSsC6NU_ADzd1QGg
CODEN IEEPAD
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/PACT58117.2023.00009
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
Accès Toulouse INP et ENVT - IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798350342543
EndPage 13
ExternalDocumentID 10364591
Genre orig-research
GrantInformation_xml – fundername: European Research Council
  funderid: 10.13039/100010663
GroupedDBID 6IE
6IL
ACM
ALMA_UNASSIGNED_HOLDINGS
APO
CBEJK
LHSKQ
RIE
RIL
ID FETCH-LOGICAL-a286t-b16c7dcdaee994e4a2b93f71b78ce1b4ad13c20db539d559afb4aca59f5b38ba3
IEDL.DBID RIE
ISICitedReferencesCount 1
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001165646800001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:03:27 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a286t-b16c7dcdaee994e4a2b93f71b78ce1b4ad13c20db539d559afb4aca59f5b38ba3
PageCount 13
ParticipantIDs ieee_primary_10364591
PublicationCentury 2000
PublicationDate 2023-Oct.-21
PublicationDateYYYYMMDD 2023-10-21
PublicationDate_xml – month: 10
  year: 2023
  text: 2023-Oct.-21
  day: 21
PublicationDecade 2020
PublicationTitle 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)
PublicationTitleAbbrev PACT
PublicationYear 2023
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssib057737293
Score 2.2427292
Snippet Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Computer languages
Energy consumption
Hardware
Multithreading
Out of order
Parallel architectures
Writing
Title CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
URI https://ieeexplore.ieee.org/document/10364591
WOSCitedRecordID wos001165646800001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NTwMhECVqPHhSY43f4eCVuiywLN5MbeOhaZumJr01A8wmvWzNduvvF2ir8eDBCyEkQDLDMBmGN4-QRymhUs5xhoUEJk0IUMBnimlROp5bVWHhE9mEHo3K-dxMdmD1hIVBxPT5DLuxm3L5fuU28aksWHhMmkWs-qHWxRastT88SkfCFSN28DiemafJS2-mIpCyGznCU6VC84tEJfmQwek_dz8jnR80Hp18-5lzcoD1BRn3-sPh-JlGew6G3bAg56gxT_upKERYig5X4Fls6DgW2AyT6bKmr9ACm4JDNmgQ6RTjj-R1h7wP-rPeG9uRIzDIy6JllhdOe-cB0RiJEnJrRKW51aVDbiV4LlyeeauE8SFsgCqMOVCmUlaUFsQlOapXNV4RyovCZnnQipBKSuMASutjipaHhXJQ16QTpbH42Na_WOwFcfPH-C05iQKPN3zO78hR22zwnhy7z3a5bh6S1r4A_meYhA
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEA2igp5UrPhtDl5TN5tkd-NNakvFtS2lQm9lksxCL1vZbv39JttW8eDBSwiBJPAmk5BM3jxC7qWEQlnLGSYSmNT-ggIuUiwVmeWxUQUmrhGbSAeDbDrVow1ZveHCIGLz-QzbodrE8t3CrsJTmffwEDQLXPU9JWUcrela2-Wj0iC5osWGIMcj_TB66kxUoFK2g0p4k6tQ_5JRaU6R3tE_5z8mrR8-Hh19nzQnZAfLUzLsdPN8-EiDR3vXrphHOtjM0W6TFsIPRfMFOBYKOgwpNn1nOi_pM9TAxmCR9SpEOsbwJ3nZIu-97qTTZxt5BAZxltTM8MSmzjpA1FqihNhoUaTcpJlFbiQ4LmwcOaOEdv7iAIVvs6B0oYzIDIgzslsuSjwnlCeJiWJvFyE9sNoCZMaFIC33A8WgLkgroDH7WGfAmG2BuPyj_Y4c9Cdv-Sx_GbxekcMAftjvY35NdutqhTdk337W82V121jwCx8-m8s
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2023+32nd+International+Conference+on+Parallel+Architectures+and+Compilation+Techniques+%28PACT%29&rft.atitle=CELLO%3A+Compiler-Assisted+Efficient+Load-Load+Ordering+in+Data-Race-Free+Regions&rft.au=Singh%2C+Sawan&rft.au=Feliu%2C+Josue&rft.au=Acacio%2C+Manuel+E.&rft.au=Jimborean%2C+Alexandra&rft.date=2023-10-21&rft.pub=IEEE&rft.spage=1&rft.epage=13&rft_id=info:doi/10.1109%2FPACT58117.2023.00009&rft.externalDocID=10364591