CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all the in-flight loads and is searched on every invalidation and cache eviction. Moreover, in a simultaneous multithreading processor (SMT), sto...
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| Vydáno v: | 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) s. 1 - 13 |
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IEEE
21.10.2023
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| Abstract | Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all the in-flight loads and is searched on every invalidation and cache eviction. Moreover, in a simultaneous multithreading processor (SMT), stores also search the LQ when writing to cache. LQ searches entail considerable energy consumption. Furthermore, the processor stalls upon encountering the LQ full or when its ports are busy. Hence, the LQ is a critical structure in terms of both energy and performance. In this work, we observe that the use of the LQ could be dramatically optimized under the guarantees of the datarace-free (DRF) property imposed by modern programming languages. To leverage this observation, we propose CELLO, a software-hardware co-design in which the compiler detects memory operations in DRF regions and the hardware optimizes their execution by safely skipping LQ searches without violating the TSO consistency model. Furthermore, CELLO allows removing DRF loads from the LQ earlier, as they do not need to be searched to detect consistency violations. With minimal hardware overhead, we show that an 8-core 2-way SMT processor with CELLO avoids almost all conservative searches to the LQ and significantly reduces its occupancy. CELLO allows i) to reduce the LQ energy expenditure by 33% on average (up to 53%) while performing 2.8% better on average (up to 18.6%) than the baseline system, and ii) to shrink the LQ size from 192 to only 80 entries, reducing the LQ energy expenditure as much as 69% while performing on par with a mainstream LQ implementation. |
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| AbstractList | Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all the in-flight loads and is searched on every invalidation and cache eviction. Moreover, in a simultaneous multithreading processor (SMT), stores also search the LQ when writing to cache. LQ searches entail considerable energy consumption. Furthermore, the processor stalls upon encountering the LQ full or when its ports are busy. Hence, the LQ is a critical structure in terms of both energy and performance. In this work, we observe that the use of the LQ could be dramatically optimized under the guarantees of the datarace-free (DRF) property imposed by modern programming languages. To leverage this observation, we propose CELLO, a software-hardware co-design in which the compiler detects memory operations in DRF regions and the hardware optimizes their execution by safely skipping LQ searches without violating the TSO consistency model. Furthermore, CELLO allows removing DRF loads from the LQ earlier, as they do not need to be searched to detect consistency violations. With minimal hardware overhead, we show that an 8-core 2-way SMT processor with CELLO avoids almost all conservative searches to the LQ and significantly reduces its occupancy. CELLO allows i) to reduce the LQ energy expenditure by 33% on average (up to 53%) while performing 2.8% better on average (up to 18.6%) than the baseline system, and ii) to shrink the LQ size from 192 to only 80 entries, reducing the LQ energy expenditure as much as 69% while performing on par with a mainstream LQ implementation. |
| Author | Feliu, Josue Acacio, Manuel E. Ros, Alberto Singh, Sawan Jimborean, Alexandra |
| Author_xml | – sequence: 1 givenname: Sawan surname: Singh fullname: Singh, Sawan email: singh.sawan@um.es organization: University of Murcia,Computer Engineering Department,Murcia,Spain – sequence: 2 givenname: Josue surname: Feliu fullname: Feliu, Josue email: jfeliu@disca.upv.es organization: Universitat Politècnica de València,Computer Engineering Department,València,Spain – sequence: 3 givenname: Manuel E. surname: Acacio fullname: Acacio, Manuel E. email: meacacio@um.es organization: University of Murcia,Computer Engineering Department,Murcia,Spain – sequence: 4 givenname: Alexandra surname: Jimborean fullname: Jimborean, Alexandra email: alexandra.jimborean@um.es organization: University of Murcia,Computer Engineering Department,Murcia,Spain – sequence: 5 givenname: Alberto surname: Ros fullname: Ros, Alberto email: aros@ditec.um.es organization: University of Murcia,Computer Engineering Department,Murcia,Spain |
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| Snippet | Efficient Total Store Order (TSO) implementations allow loads to execute speculatively out-of-order. To detect order violations, the load queue (LQ) holds all... |
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| SubjectTerms | Computer languages Energy consumption Hardware Multithreading Out of order Parallel architectures Writing |
| Title | CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions |
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