QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not...
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| Veröffentlicht in: | Proceedings - International Symposium on Computer Architecture S. 944 - 957 |
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IEEE
01.06.2021
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| ISSN: | 2575-713X |
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| Abstract | True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not every computing system is equipped with dedicated TRNG hardware, limiting the application space and security guarantees for such systems. To open the application space and enable security guarantees for the overwhelming majority of computing systems that do not necessarily have dedicated TRNG hardware (e.g., processing-in-memory systems), we develop QUAC-TRNG, a new high-throughput TRNG that can be fully implemented in commodity DRAM chips, which are key components in most modern systems.QUAC-TRNG exploits the new observation that a carefully-engineered sequence of DRAM commands activates four consecutive DRAM rows in rapid succession. This QUadruple ACtivation (QUAC) causes the bitline sense amplifiers to non-deterministically converge to random values when we activate four rows that store conflicting data because the net deviation in bitline voltage fails to meet reliable sensing margins.We experimentally demonstrate that QUAC reliably generates random values across 136 commodity DDR4 DRAM chips from one major DRAM manufacturer. We describe how to develop an effective TRNG (QUAC-TRNG) based on QUAC. We evaluate the quality of our TRNG using the commonly-used NIST statistical test suite for randomness and find that QUAC-TRNG successfully passes each test. Our experimental evaluations show that QUAC-TRNG reliably generates true random numbers with a throughput of 3.44 Gb/s (per DRAM channel), outperforming the state-of-the-art DRAM-based TRNG by 15.08× and 1.41× for basic and throughput-optimized versions, respectively. We show that QUAC-TRNG utilizes DRAM bandwidth better than the state-of-the-art, achieving up to 2.03× the throughput of a throughput-optimized baseline when scaling bus frequencies to 12 GT/s. |
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| AbstractList | True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not every computing system is equipped with dedicated TRNG hardware, limiting the application space and security guarantees for such systems. To open the application space and enable security guarantees for the overwhelming majority of computing systems that do not necessarily have dedicated TRNG hardware (e.g., processing-in-memory systems), we develop QUAC-TRNG, a new high-throughput TRNG that can be fully implemented in commodity DRAM chips, which are key components in most modern systems.QUAC-TRNG exploits the new observation that a carefully-engineered sequence of DRAM commands activates four consecutive DRAM rows in rapid succession. This QUadruple ACtivation (QUAC) causes the bitline sense amplifiers to non-deterministically converge to random values when we activate four rows that store conflicting data because the net deviation in bitline voltage fails to meet reliable sensing margins.We experimentally demonstrate that QUAC reliably generates random values across 136 commodity DDR4 DRAM chips from one major DRAM manufacturer. We describe how to develop an effective TRNG (QUAC-TRNG) based on QUAC. We evaluate the quality of our TRNG using the commonly-used NIST statistical test suite for randomness and find that QUAC-TRNG successfully passes each test. Our experimental evaluations show that QUAC-TRNG reliably generates true random numbers with a throughput of 3.44 Gb/s (per DRAM channel), outperforming the state-of-the-art DRAM-based TRNG by 15.08× and 1.41× for basic and throughput-optimized versions, respectively. We show that QUAC-TRNG utilizes DRAM bandwidth better than the state-of-the-art, achieving up to 2.03× the throughput of a throughput-optimized baseline when scaling bus frequencies to 12 GT/s. |
| Author | Patel, Minesh Yaglikci, A. Giray Luo, Haocong Nisa Bostanci, F. Kim, Jeremie S. Ergin, Oguz Mutlu, Onur Olgun, Ataberk Vijaykumar, Nandita |
| Author_xml | – sequence: 1 givenname: Ataberk surname: Olgun fullname: Olgun, Ataberk organization: ETH Zürich – sequence: 2 givenname: Minesh surname: Patel fullname: Patel, Minesh organization: ETH Zürich – sequence: 3 givenname: A. Giray surname: Yaglikci fullname: Yaglikci, A. Giray organization: ETH Zürich – sequence: 4 givenname: Haocong surname: Luo fullname: Luo, Haocong organization: ETH Zürich – sequence: 5 givenname: Jeremie S. surname: Kim fullname: Kim, Jeremie S. organization: ETH Zürich – sequence: 6 givenname: F. surname: Nisa Bostanci fullname: Nisa Bostanci, F. organization: ETH Zürich – sequence: 7 givenname: Nandita surname: Vijaykumar fullname: Vijaykumar, Nandita organization: ETH Zürich – sequence: 8 givenname: Oguz surname: Ergin fullname: Ergin, Oguz organization: TOBB University of Economics and Technology – sequence: 9 givenname: Onur surname: Mutlu fullname: Mutlu, Onur organization: ETH Zürich |
| BookMark | eNotj1FPwjAcxKvRREA_gT70Cwz_bdd19W2ZCiSIAUfiGym2YzWsXbpNw7d3Cd7LPdwvl7sxunLeGYQeCEwJAfm4-MgzToHQKQVKpgAg0gs0JknCYzZIXKIR5YJHgrDPGzRu228AIiVPRsivt1keFZvV7AnP7aGKiir4_lA1fYeL0Bu8UU77Gq_6em8Cnhlnguqsd3jbWnfA617p0DfHAfS_OPvq7M85tg7nvq69tt0JP2-yN5xXtmlv0XWpjq25-_cJ2r6-FPk8Wr7PFnm2jBRNeRelinNjSslA8WG1LEEmRDAhYh0rBWVi0uGmYqrkjGqtKOyB7GMtICkNTSiboPtzrzXG7JpgaxVOOxlLKSRnfwc2WnI |
| CODEN | IEEPAD |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1109/ISCA52012.2021.00078 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE/IET Electronic Library (IEL) (UW System Shared) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE/IET Electronic Library (IEL) (UW System Shared) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISBN | 1665433337 9781665433334 |
| EISSN | 2575-713X |
| EndPage | 957 |
| ExternalDocumentID | 9499795 |
| Genre | orig-research |
| GroupedDBID | 23M 29F 29O 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR AAWTH ACGFS ADZIZ ALMA_UNASSIGNED_HOLDINGS APO BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP IPLJI M43 OCL RIE RIL RIO ZY4 |
| ID | FETCH-LOGICAL-a285t-8a55eef930a57139f096173774d4aa0f6e8000a3af532dda20b01b4d706fe2623 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 22 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000702275600069&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 02:24:06 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a285t-8a55eef930a57139f096173774d4aa0f6e8000a3af532dda20b01b4d706fe2623 |
| PageCount | 14 |
| ParticipantIDs | ieee_primary_9499795 |
| PublicationCentury | 2000 |
| PublicationDate | 2021-June |
| PublicationDateYYYYMMDD | 2021-06-01 |
| PublicationDate_xml | – month: 06 year: 2021 text: 2021-June |
| PublicationDecade | 2020 |
| PublicationTitle | Proceedings - International Symposium on Computer Architecture |
| PublicationTitleAbbrev | ISCA |
| PublicationYear | 2021 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0019956 |
| Score | 2.4913263 |
| Snippet | True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 944 |
| SubjectTerms | Bandwidth DRAM chips Hardware Limiting Machine learning NIST Throughput |
| Title | QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips |
| URI | https://ieeexplore.ieee.org/document/9499795 |
| WOSCitedRecordID | wos000702275600069&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1dS8MwFA3b8MGnqZv4TR58NFu_0jS-jepU0DJnhb2NNB9Y0HZsq_59k7SbCL74FkqgcC_hnpuccw8AlyFmJAgNVcpVBAWeq1CmIo6E9FzOlcYkmR2Z_0iSJJrN6KQFrrZaGCmlJZ_JgVnat3xR8spclQ3NIBVCcRu0CQlrrdb2xcAoNBtpnOvQ4cNLPMK6uBmtlecObCn8ZaBi68e4-78_74H-jxAPTrYlZh-0ZHEAuhsnBtgczB4oNTCNUTpN7q6hYW6gtLbf0dtguqwknLJClB8wsf4fsJ41bVICLWUAPldMLKvFu95YfsER33iewbyARkJSCg3W4c109ATjt3yx6oPX8W0a36PGSgExL8JrFDGMpVTUdxjWbSlVxumF-Br7iYAxR4VSA0eH-Uxh3xOCeeZ-NAsEcUIlPQ2RDkGnKAt5BKDGgDLCurFRuhfjktMo8zFVfuYIGgQ0OwY9E7_5op6WMW9Cd_L351OwaxJUk6_OQGetY3IOdvjnOl8tL2yKvwFCQadG |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1dS8MwFA1zCvo0dYrf5sFHs_UrbePbqM4NtzJnhb2NNB840HZsq_59k7SbCL74FkqgcC_hnpuccw8ANz6mgedrqpQtA-Q5tkSpDBniwrEZkwqTpGZk_iCI43AyIaMauN1oYYQQhnwmWnpp3vJ5zgp9VdbWg1QCgrfAtnbOqtRamzcDrdGsxHG2Rdr9l6iDVXnTaivHbpli-MtCxVSQbuN__94HRz9SPDjaFJkDUBPZIWisvRhgdTSbIFfQNELJOH68g5q7gZLSgEdtg8miEHBMM55_wNg4gMBy2rROCjSkAfhcUL4o5u9qY_4FO2ztegZnGdQikpwruA7vx50hjN5m8-UReO0-JFEPVWYKiDohXqGQYiyEJK5FsWpMidReL4Gr0B_3KLWkLxR0tKhLJXYdzqmjb0hTjweWL4WjQNIxqGd5Jk4AVChQhFi1NlJ1Y0wwEqYuJtJNLU48j6SnoKnjN52X8zKmVejO_v58DXZ7yXAwHfTjp3Owp5NVUrEuQH2l4nMJdtjnarZcXJl0fwMn3qqP |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=Proceedings+-+International+Symposium+on+Computer+Architecture&rft.atitle=QUAC-TRNG%3A+High-Throughput+True+Random+Number+Generation+Using+Quadruple+Row+Activation+in+Commodity+DRAM+Chips&rft.au=Olgun%2C+Ataberk&rft.au=Patel%2C+Minesh&rft.au=Yaglikci%2C+A.+Giray&rft.au=Luo%2C+Haocong&rft.date=2021-06-01&rft.pub=IEEE&rft.eissn=2575-713X&rft.spage=944&rft.epage=957&rft_id=info:doi/10.1109%2FISCA52012.2021.00078&rft.externalDocID=9499795 |