A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an I...

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Bibliographic Details
Published in:2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Nacci, Alessandro Antonio, Rana, Vincenzo, Bruschi, Francesco, Sciuto, Donatella, Beretta, Ivan, Atienza, David
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 29.05.2013
IEEE
Series:ACM Conferences
Subjects:
Algorithm design and analysis
Computer architecture
Estimation
Field programmable gate arrays
Hardware
Hardware > Electronic design automation > High-level and register-transfer level synthesis
High Level Synthesis
Iterative stencil loops
Performance and Area Estimation
Symbolic Execution
System-on-chip
Theory of computation > Models of computation > Concurrency
Theory of computation > Models of computation > Concurrency > Parallel computing models
Throughput
symbolic execution
high level synthesis
iterative stencil loops
performance and area estimation
ISBN:1450320716, 9781450320719
ISSN:0738-100X
Online Access:Get full text
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Summary:The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488797