Nacci, A. A., Rana, V., Bruschi, F., Sciuto, D., Beretta, I., & Atienza, D. (2013, May 29). A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6. https://doi.org/10.1145/2463209.2488797
Citace podle Chicago (17th ed.)Nacci, Alessandro Antonio, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, a David Atienza. "A High-level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices." 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) 29 May. 2013: 1-6. https://doi.org/10.1145/2463209.2488797.
Citace podle MLA (9th ed.)Nacci, Alessandro Antonio, et al. "A High-level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices." 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 29 May. 2013, pp. 1-6, https://doi.org/10.1145/2463209.2488797.